SOC Physical Design Engineer: Power, Timing & Integration

Apple Inc.; Austin (TX); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Apple Inc. in Austin, Texas is seeking a seasoned physical design engineer to implement SOC blocks from netlist to tape-out in advanced nodes.

You will collaborate with RTL and FE teams to understand architecture, drive physical design, and optimize power, performance, and area while improving methodologies and flows. The role requires strong scripting (Perl, Shell, TCL) and experience with EDA tools such as Innovus, IC Compiler, Primetime, and Calibre.

Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
• 5 years of experience in the job offered or related occupation.
• Experience with Electronic Design Automation (EDA) tools such as Innovus or IC Compiler, Primetime or Calibre.
• Experience in synthesis, automated place and route, or verification flows, including logic equivalency, low power verification, or physical design verification.
• Understanding timing convergence and low power verification constraints.
• Knowledge of clock gating, power gating, or multi‑voltage designs to optimize power and area.
• Proficiency with HDL to describe digital circuits.
• Automation with scripting (Perl, Shell, Makefiles, TCL).
• Block and IP level floorplanning: pin assignment and macro placement.
• Routing and congestion analysis.

Responsibilities

• Perform physical design implementation of SOC blocks from netlist to tape-out in advanced technology nodes.
• Collaborate with RTL design to understand data flow and place memories and macros.
• Implement clock and power distribution, routing, and packing for the block.
• Optimize for area, power, and timing convergence; resolve congestion hotspots.
• Run STA, IR/IVD, DRC/LVS checks and clean up violations.
• Develop scripts to extract trends from design data and improve flows.
• Interact with integration, timing, and electrical analysis teams.

Skills

Scripting: Perl

Scripting: Shell

Scripting: TCL

Digital design knowledge

Education

Master's degree in Electrical Engineering or related field

Tools

Innovus

IC Compiler

Primetime

Calibre

Job description

Apple Inc. in Austin, Texas is seeking a seasoned physical design engineer to implement SOC blocks from netlist to tape-out in advanced nodes.

You will collaborate with RTL and FE teams to understand architecture, drive physical design, and optimize power, performance, and area while improving methodologies and flows. The role requires strong scripting (Perl, Shell, TCL) and experience with EDA tools such as Innovus, IC Compiler, Primetime, and Calibre.