Campus Packaging Architect – AI Data Center Silicon

MediaTek; San Jose (CA); On-site; USD 122,000 - 213,000; Full time

Benefits offered by this job

Health insurance

Life insurance

Disability insurance

Savings plan (401K)

Paid holidays

Sick leave

Vacation time

Parental leave

Job summary

MediaTek, the world‑class fabless IC design leader, is seeking a graduate student to join the Data Center Product Architecture and Technology team. You will help develop and evaluate packaging solutions for next‑gen AI silicon, and perform signal and power integrity analyses for high‑speed interfaces.

Location: San Jose, California (on‑site) or Portland, Oregon (on‑site). You will work with cross‑functional teams to improve packaging solutions, analyze SI/PI, and contribute to future data center

Qualifications

• MS in Electrical Engineering or related field expected by 2027.
• Solid understanding of VLSI package design and silicon interactions.
• Experience with transient and frequency domain analysis.
• Good understanding of silicon packaging and deep submicron silicon process.
• Proficient with package layout tools (Cadence Allegro) and SI/PI tools (HFSS).

Responsibilities

• Develop and evaluate packaging solutions for next generation data center and AI silicon products.
• Signal and Power integrity analysis for high speed interfaces; Power delivery network design.
• Collaborate with cross functional teams to improve packaging solution in key vectors including performance and form factor.
• Understand Industry and technology trends.

Skills

VLSI packaging

Silicon interactions

Transient analysis

Frequency domain analysis

Silicon packaging experience

Education

MS in Electrical Engineering

Tools

Cadence Allegro

Ansys HFSS

Job description

MediaTek, the world‑class fabless IC design leader, is seeking a graduate student to join the Data Center Product Architecture and Technology team. You will help develop and evaluate packaging solutions for next‑gen AI silicon, and perform signal and power integrity analyses for high‑speed interfaces.

Location: San Jose, California (on‑site) or Portland, Oregon (on‑site). You will work with cross‑functional teams to improve packaging solutions, analyze SI/PI, and contribute to future data center