Senior 3D Packaging Architect for AI Accelerators

Entrada Ventures; Palo Alto (CA); Hybrid; USD 180,000 - 270,000; Full time

Job summary

Entrada Ventures, a Silicon Valley–based startup, seeks a Senior Packaging Engineer to architect and deliver advanced multi-die IC packages for high-performance AI accelerators. You will drive package architecture, substrate design, manufacturability, and vendor engagement in a fast-paced environment.

You will partner with IC design, physical design, and board teams to meet system-level needs, evaluate new packaging technologies, and support bring-up and qualification across internal sites and

Qualifications

• B.S./M.S. in Electrical Engineering or related field.
• Experience with multi-die package design and UCIe integration.
• Experience interfacing with TSMC/OSAT and managing subcontractors.

Responsibilities

• Select and design optimal multi-die package types balancing electrical performance, thermal behavior, cost, and manufacturability.
• Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.
• Define substrate stack-ups, bump pitch, ball pitch, routing, via structures, and material choices for performance and manufacturability.
• Perform high-speed signal escaping, routing and power distribution network design.
• Manage subcontractors and collaborate with TSMC and OSAT on bumping and packaging flows.
• Partner with IC design, physical design, SI/PI, and board teams for system-level needs.
• Evaluate emerging packaging technologies and drive adoption for next-generation products.
• Support package-level bring-up, failure analysis, debug and qualification.

Skills

Multi-die packaging

UCIe integration

SI/PI concepts

Package modeling tools

Subcontractor management

Vendor engagement with TSMC/OSAT

Education

B.S./M.S. in Electrical Engineering or related field

Tools

HFSS

Sigrity

Job description

Entrada Ventures, a Silicon Valley–based startup, seeks a Senior Packaging Engineer to architect and deliver advanced multi-die IC packages for high-performance AI accelerators. You will drive package architecture, substrate design, manufacturability, and vendor engagement in a fast-paced environment.

You will partner with IC design, physical design, and board teams to meet system-level needs, evaluate new packaging technologies, and support bring-up and qualification across internal sites and