Packaging Architect

MediaTek Research Lab Inc.; San Jose (CA); On-site; USD 171,000 - 272,000; Full time

Benefits offered by this job

Comprehensive health insurance

401(k) plan

Paid holidays and leave

Job summary

MediaTek Research Lab Inc. in San Jose is looking for an experienced Packaging Architect specializing in advanced semiconductor packaging technologies like 2.5D/3D/3.5D. This position involves collaboration with various teams to develop innovative packaging solutions for automotive and computing applications.

The ideal candidate should possess over eight years of hands-on experience and excellent communication skills. Competitive salary range is $171,000 to $272,000, plus benefits including health insurance and a 401(k).

Qualifications

• 8+ years in advanced semiconductor package architecture.
• Hands-on experience with 2D, 2.5D, and 3D packaging.
• Strong understanding of high-speed interface impact on packaging.

Responsibilities

• Identify optimal package architecture balancing performance.
• Collaborate on silicon-disaggregation and chiplet strategies.
• Perform trade-off analysis impacting product metrics.
• Define packaging technology and material requirements.
• Engage with product team and customers on emerging architectures.

Skills

Advanced semiconductor package architecture (2.5D/3D/3.5D)

Power-signal integrity

Thermal-mechanical engineering

High-speed interfaces (SERDES, PCIe)

Communication skills

Tools

EDA tools

CAD tools

Job description

MediaTek is seeking a talented and experienced technical leader with expertise in Packaging Architect, specifically 2.5D/3D/3.5D and STCO. This role involves close collaboration with cross-functional teams, including IP, ASIC Design, Package Design, Signal Integrity, Power Integrity, Thermal, thermomechanical, product engineering, Test, and system team. The goal is to develop advanced packaging architecture and to guide development of innovative packaging solutions for automotive, datacenter/HPC, and computing applications. The ideal candidate will play a key role in identifying the optimal package architecture and key packaging technologies, establishing 3rd party relationships, communicating with partners and addressing challenges in areas such as 2.5D/3D/3.5D and System technology optimization with advanced Si nodes, including but not limited to CoWoS-S/R/L, EMIB/EMIB-T, SoIC, HBM, FCBGA, and HBPOP. The candidate should demonstrate ownership, high standards, strategic thinking, and customer obsession.

Roles and Responsibilities

• Identify the optimal package architecture by balancing electrical, thermal, and mechanical performance, meeting project’s timeline.
• Working closely with internal and external partners on silicon-disaggregation and other chiplet strategies for advanced packages, including emerging-memory chiplet integration.
• Perform a trade-off analysis across silicon layout, die-to-die connectivity options, and package design/technology, evaluating their impact on key product metrics, including performance, cost, manufacturability, power efficiency, and form factor.
• Identifying critical elements for packaging roadmap, Partner with supply chain engineering experts to define packaging technology and material requirements for substrate fabrication, assembly, and raw material vendors.
• Stay informed about emerging packaging architectures by engaging with the product team and customers in the data center and high-end compute segments.
• Continuously monitor the competitive landscape in packaging technologies and solutions.

Main Requirements and Qualifications

• Extensive hands‑on experience (8+ years) in advanced semiconductor package architecture, including 2.5D/3D/3.5D, CoWoS-S/R/L, EMIB/EMIB-T, SoIC, HBM, FCBGA, HBPOP, and related technologies.
• Extensive experience in characterization and design of 2D, 2.5D, & 3D flip‑chip & wafer‑scale packaging solutions; experience in the areas of power‑signal integrity, thermal‑mechanical & system engineering domains.
• Proven track record of bringing up successful packages/products with high power and high bandwidth applications from inception to product introduction.
• Extensive experience with high‑speed interfaces, including SERDES, PCIe, die‑to‑die (D2D) interconnects and CPO & CPC, with a strong understanding of their impact on packaging technology choices, such as substrate selection, interconnect architecture, signal integrity, CPO & CPC integration, and thermal considerations.
• Experience in HBM on package integration, DDR integration, and working knowledge of various memory types.
• Experience in various EDA & CAD tools.
• Excellent communication skills.
• About 10‑15% international travel required.
• Salary range: $171,000- $272,000.
• Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, company paid holidays, sick leave, vacation time, parental leave, 401(k) and more.
• MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.