Cache Coherent Interconnects Senior Logic Engineer (Hybrid)

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 218,500; Full time

Job summary

A technology company is seeking a Senior Logic Design Engineer to design CPU on-chip and off-chip interconnect networks. Responsibilities include high-performance RTL coding, logic debug, and collaboration with verification teams. The ideal candidate has a Master’s Degree and over 5 years of experience in semiconductor designs. Strong Verilog expertise and a background in computer architecture and cache coherency are essential. This position offers competitive salary and equity opportunities.

Qualifications

• 5+ years of experience in processor or related high-performance semiconductor designs.
• Deep understanding of ASIC design flow including RTL design and verification.
• Strong background in computer architecture and cache coherency.

Responsibilities

• Own and deliver a specific unit on the chip.
• Write high performance and low power RTL.
• Collaborate with verification team for correctness.

Skills

Verilog expertise

Strong communication skills

Mentoring experience

Education

Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science

Tools

ASIC design tools

Job description

A technology company is seeking a Senior Logic Design Engineer to design CPU on-chip and off-chip interconnect networks. Responsibilities include high-performance RTL coding, logic debug, and collaboration with verification teams. The ideal candidate has a Master’s Degree and over 5 years of experience in semiconductor designs. Strong Verilog expertise and a background in computer architecture and cache coherency are essential. This position offers competitive salary and equity opportunities.