ASIC Verification Engineer

People Consultancy Services (PCS); Sunnyvale (CA); Hybrid; USD 150,000 - 210,000; Full time

Job summary

People Consultancy Services (PCS) is seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team in a hybrid Sunnyvale setting. You will own block-level verification, craft test plans, and drive coverage closure for complex SoCs.

You will build and refine advanced UVM environments, perform constrained random testing, and debug using industry tools. Collaboration with cross-functional teams is essential to deliver robust ASIC/SoC designs.

Qualifications

• 5+ years of ASIC/SoC verification experience with ownership from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including building environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on test planning, coverage analysis, and debugging of complex SoC designs.

Responsibilities

• Own and drive block-level or subsystem verification, from test plan to coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments (agents, sequences, scoreboards, etc.).
• Perform constraint-driven random testing and debug complex SoC designs to meet coverage goals.
• Analyze simulation results using Cadence Xcelium, Synopsys VCS, and Mentor Questa, debugging waveforms to validate functionality.
• Collaborate with cross-functional teams to resolve issues and ensure high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM

Test planning

Coverage analysis

Assertions (SVA)

Debugging complex SoCs

Constraint-driven random testing

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

This is a Hybrid role based in Sunnyvale, CA with an expectation that you’ll be in the office 2 days per week.

Position Summary

We are seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team.

Key Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Required Skills and Qualifications

• 5+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands‑on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Preferred Skills and Experience

• Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
• Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
• Exposure to emulation environments, hardware acceleration, or traffic‑model integration.
• Knowledge of coverage analytics, regression dashboards, and continuous‑integration flows (e.g., Jenkins).
• Understanding of low‑power (UPF) or formal verification methodologies.
• Own and drive block-level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure
• Experience with post‑silicon bring-up and debug is a plus.
• Familiarity with emulation environments and debug flows is desirable.