SoC Verification Engineer

Yochana; United States; On-site; USD 120,000 - 160,000; Full time

Job summary

Yochana is seeking a senior ASIC verification engineer to own block-level verification across multiple complex designs. The role requires end-to-end UVM experience from scratch and hands-on work with high-speed protocols.

You will develop testbenches, sequences, agents, and coverage models in SystemVerilog, perform waveform analysis, and collaborate with customer teams to align verification with top-level testbenches.

Qualifications

• End-to-end UVM experience from scratch.
• 6 to 10+ years of ASIC verification in complex designs.
• Expert in SystemVerilog and UVM; testbenches and components built from scratch.
• Hands-on verification with high-speed protocols including Ethernet.
• Experience debugging with industry simulators and waveform analysis.

Responsibilities

• Own block-level verification of 4-5 complex design blocks per project.
• Develop and maintain verification components, sequences, agents, scoreboards, and coverage models from scratch in SystemVerilog/UVM.
• Execute directed and constrained-random tests; drive functional and code coverage closure.
• Apply knowledge of UCIe 2.0, PCIe, and Ethernet to verify architectural features.
• Collaborate with customer engineering teams and internal leads to align with top-level testbench.
• Perform waveform analysis, protocol debugging, root-cause analysis, and regression triage.

Skills

End-to-end ASIC verification

SystemVerilog

UVM

From scratch testbench development

Waveform analysis

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Must Requirement

End-to-end UVM experience from scratch

Key Responsibilities

• Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.
• Testbench & Component Development: Build and maintain verification components, test sequences, agents, scoreboards, and functional coverage models from scratch using System Verilog and UVM.
• Verification Execution: Execute directed and constrained-random test scenarios, perform rigorous test debugging, and drive functional and code coverage closure.
• Protocol Application: Apply deep working knowledge of advanced industry protocols such as UCIe (Universal Chiplet Interconnect Express) 2.0, PCIe, and Ethernet to verify complex architectural features.
• Collaboration: Interface smoothly with customer engineering teams and internal project leads, ensuring block-level verification aligns with the customer-owned top-level testbench infrastructure.
• Debugging & Triage: Perform in-depth waveform analysis, protocol debugging, root-cause analysis, and regression triage using industry-standard simulators.

Required Qualifications & Skills

• Experience: 6 to 10+ years of relevant hands-on ASIC verification experience in complex digital designs.
• Methodologies: Expert-level proficiency in SystemVerilog and UVM, with a proven history of developing testbenches, test sequences, agents, and other components from scratch.
• Protocol Knowledge: Hands-on verification experience with one or more high-speed protocols:
• Ethernet (MAC/PCS/PMA layers)
• Domain Background: Proven track record working on complex networking silicon, Switches, NICs, or high-performance interconnect ASICs.
• Debugging Skills: Strong expertise in waveform analysis, protocol debugging, root-cause analysis, and regression triage using simulators (Synopsys VCS, Cadence Xcelium, or Mentor Questa).
• Soft Skills: Strong problem-solving abilities, solid communication skills, and the capability to work autonomously in a collaborative, customer-facing environment.