ASIC Verification Engineer: 26-02766

Akraya, Inc.; Allentown (Lehigh County); On-site; USD 96,000 - 99,000; Full time

Job summary

Akraya, Inc. is seeking an experienced ASIC Verification Engineer for Cisco's Silicon One team, with 5–12 years in SV/UVM, to support next-generation SoC designs.

The role involves building verification environments, testbenches, and debugging complex silicon issues, collaborating across design teams, and facilitating post-silicon bring-up.

Qualifications

• 5–12 years of ASIC/SoC verification experience with strong hands-on SystemVerilog and UVM expertise.
• Proven experience developing UVM testbenches, verification plans, and verification infrastructure from block to system level.
• Experience with timing/gate-level simulation, complex debug, and C programming for firmware/post-silicon bring-up.
• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, Communications Engineering, or related field.

Responsibilities

• Develop and maintain UVM-based verification environments and testbenches for ASIC/SoC designs.
• Create verification plans and develop assertions, agents, traffic generators, scoreboards, and test cases.
• Perform SystemVerilog coding, simulation, debug, and failure analysis.
• Collaborate with design and cross-functional teams to improve design testability and verification coverage.
• Lead complex verification/debug efforts and support timing, gate-level, and post-silicon bring-up activities.

Skills

SystemVerilog

UVM

ASIC/SoC verification

Verification testbench

RTL/Design verification

Education

Bachelor's/Master's in Electrical/Computer/Communications Engineering or related field

Tools

Python

Perl

C programming

Job description

Primary kills: System Verilog (Expert), UVM (Expert), ASIC/SoC Verification (Advanced), Verification Testbench (Advanced), RTL/Design Verification (Advanced) Contract Type: W2 Only Duration: 12 Months Location: Allentown, PA (100% Onsite) or Carlsbad, CA (100% onsite) Pay Range: $70-$72/hr on W2

Job Summary

We are seeking an experienced ASIC Verification Engineer with 5–12 years of experience to support next-generation SoC designs for Cisco's Silicon One team. The ideal candidate will have strong hands-on experience with System Verilog, UVM-based verification, testbench development, and block-to-system-level verification.

Key Responsibilities

• Develop and maintain UVM-based verification environments and testbenches for ASIC/SoC designs.
• Create verification plans and develop assertions, agents, traffic generators, scoreboards, and test cases.
• Perform System Verilog coding, simulation, debug, and failure analysis.
• Collaborate with design and cross-functional teams to improve design testability and verification coverage.
• Lead complex verification/debug efforts and support timing, gate-level, and post-silicon bring-up activities.

Must-Have Skills

• 5–12 years of ASIC/SoC verification experience with strong hands-on System Verilog and UVM expertise.
• Proven experience developing UVM testbenches, verification plans, and verification infrastructure from block to system level.
• Experience with timing/gate-level simulation, complex debug, and C programming for firmware/post-silicon bring-up.
• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, Communications Engineering, or related field.

Industry Experience

• Formal verification and automation using Python or Perl.
• High-speed protocols such as PCIe, UCIe, etc.
• Analog debug, DAC/client calibration, and white-box verification.
• Experience with AI-based CAD/verification efficiency initiatives.