SoC Verification Engineer

VDart; Chesterbrook (PA); On-site; USD 120,000 - 170,000; Full time

Job summary

VDart seeks an experienced ASIC verification engineer with 6–10+ years of hands-on ASIC verification experience. You will own block-level verification, develop verification components from scratch, and drive coverage closure using SystemVerilog and UVM.

You will work with customers and internal leads to ensure alignment with the top-level testbench infrastructure. Expertise in SystemVerilog/UVM and testbench development, plus hands-on protocol knowledge (Ethernet, PCIe, UCIe 2.0) is required.

Qualifications

• 6 to 10+ years of hands-on ASIC verification experience in complex digital designs.
• Expert-level SystemVerilog and UVM, with a proven history of developing testbenches and components from scratch.
• Hands-on verification experience with one or more high-speed protocols such as Ethernet, PCIe, or similar.

Responsibilities

• Block-Level Verification Ownership: take technical ownership of verifying 4-5 blocks per project.
• Testbench & Component Development: build and maintain verification components, sequences, agents, scoreboards, and coverage models from scratch.
• Verification Execution: run directed and constrained-random tests, debug failures, and drive coverage closure.
• Protocol Application: apply knowledge of high-speed protocols (Ethernet, PCIe, UCIe 2.0) for architectural verification.
• Collaboration: interface with customer teams and internal leads to align with top-level testbenches.
• Debugging & Triage: perform waveform analysis, protocol debugging, root-cause analysis, and regression triage.

Skills

SystemVerilog

UVM

Testbench development

Constrained-random testing

Waveform analysis

Debugging

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Must Requirement

End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.)

Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise.

Key Responsibilities

• Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.
• Testbench & Component Development: Build and maintain verification components, test sequences, agents, scoreboards, and functional coverage models from scratch using System Verilog and UVM.
• Verification Execution: Execute directed and constrained-random test scenarios, perform rigorous test debugging, and drive functional and code coverage closure.
• Protocol Application: Apply deep working knowledge of advanced industry protocols such as UCIe (Universal Chiplet Interconnect Express) 2.0, PCIe, and Ethernet to verify complex architectural features.
• Collaboration: Interface smoothly with customer engineering teams and internal project leads, ensuring block-level verification aligns with the customer-owned top-level testbench infrastructure.
• Debugging & Triage: Perform in-depth waveform analysis, protocol debugging, root-cause analysis, and regression triage using industry-standard simulators.

Required Qualifications & Skills

• Experience: 6 to 10+ years of relevant hands-on ASIC verification experience in complex digital designs.
• Methodologies: Expert-level proficiency in SystemVerilog and UVM, with a proven history of developing testbenches, test sequences, agents, and other components from scratch.
• Protocol Knowledge: Hands-on verification experience with one or more high-speed protocol

o Ethernet (MAC/PCS/PMA layers)

• Domain Background: Proven track record working on complex networking silicon, Switches, NICs, or high-performance interconnect ASICs.
• Debugging Skills: Strong expertise in waveform analysis, protocol debugging, root-cause analysis, and regression triage using simulators (Synopsys VCS, Cadence Xcelium, or Mentor Questa).
• Soft Skills: Strong problem-solving abilities, solid communication skills, and the capability to work autonomously in a collaborative, customer-facing environment.