ASIC Physical Design Co-op: Data-Driven PPA & PnR

NOKIA; San Jose (CA); Hybride; USD 34 000 - 48 000; Plein temps

Résumé du poste

Nokia of America is seeking an ASIC PD Coop in the NI ON Comp R&D ASICs & Architecture 4B group. You will analyze PPA metrics, build dashboards, and automate data tasks to support chip tape-outs in a Hybrid role based in San Jose, CA.

The candidate should be pursuing a Bachelor's or Master's in EE or CE and be comfortable collaborating across teams while learning new EDA/PNR workflows. The internship runs 4–8 months with start dates in Jan, May, or Aug 2027.

Qualifications

• Pursuing a Bachelor's or Master's in Electrical/Computer Engineering.
• Experience with data mining and visualization tools is preferred.
• Familiarity with ASIC design and physical design workflows is an asset.
• Strong problem-solving and analytical skills.
• Great communication and collaboration abilities.
• Ability to work independently and manage multiple tasks.
• Proficiency in Python or C++ is advantageous.
• Knowledge of EDA tools is a plus.
• Self-starter with proactive learning mindset.

Responsabilités

• Apply data mining and analytics to extract insights from PPA metrics and workflows.
• Develop and maintain PPA dashboards to visualize trends and opportunities.
• Automate data collection and analysis for internal PnR trials.
• Perform power estimation and analysis using data-driven methods.
• Conduct timing analysis with STA tools and correlate with PPA data.
• Collaborate with cross-functional teams to support physical design activities.
• Stay updated on industry trends to keep designs competitive.
• Document findings and communicate recommendations clearly.

Connaissances

Data analytics

Python

C++

Team collaboration

Formation

Bachelor's or Master's in EE/CE

US accredited university

Outils

STA tools

EDA tools

Description du poste

Nokia of America is seeking an ASIC PD Coop in the NI ON Comp R&D ASICs & Architecture 4B group. You will analyze PPA metrics, build dashboards, and automate data tasks to support chip tape-outs in a Hybrid role based in San Jose, CA.

The candidate should be pursuing a Bachelor's or Master's in EE or CE and be comfortable collaborating across teams while learning new EDA/PNR workflows. The internship runs 4–8 months with start dates in Jan, May, or Aug 2027.