Co-op: Mixed-Signal Circuit Design (High-Speed Analog)

Nokia; San Jose (CA); On-site; USD 34,000 - 55,000; Full time

Job summary

Nokia invites candidates currently pursuing a master’s degree or PhD in Electrical Engineering or Computer Engineering to join our team onsite in San Jose, CA for a 4+ month period from January 2027 to May 2027. You will design, simulate, and optimize high-speed analog circuits, including ADCs and DACs, and draft precise layout floor plans to maximize performance.

The role emphasizes exploring circuit topologies, behavior modeling, and collaboration with experienced engineers in a fast-paced

Qualifications

• Candidate must be pursuing a master's or PhD in EE/CE at a US-accredited school.
• Experience with analog/mixed-signal IPs and deep submicron CMOS is desirable.
• Familiarity with layout effects and device physics is preferred.

Responsibilities

• Design, implement, and simulate high-speed analog circuits including ADCs and DACs.
• Create layout floor plans to optimize overall performance.
• Explore trade-offs across circuit topologies.

Skills

Analog/Mixed-signal IPs

Device physics

Verilog-A/Verilog-AMS

Education

Master's or PhD in Electrical Engineering or Computer Engineering (US-accredited school)

Tools

Cadence Virtuoso

Spectre

Incisive

Calibre

EMX

Totem EM/IR

Job description

Nokia invites candidates currently pursuing a master’s degree or PhD in Electrical Engineering or Computer Engineering to join our team onsite in San Jose, CA for a 4+ month period from January 2027 to May 2027. You will design, simulate, and optimize high-speed analog circuits, including ADCs and DACs, and draft precise layout floor plans to maximize performance.

The role emphasizes exploring circuit topologies, behavior modeling, and collaboration with experienced engineers in a fast-paced