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Apple in Cupertino, California, seeks a Senior ASIC Physical Design PPA Engineer to join the Digital Design Engineering group. You will partner with CAD, design, power and post-silicon teams to drive automation, scalability and reliability of PPA regression, delivering robust silicon for customers.
The role requires a BS and at least 3 years in the industry, strong scripting (Perl/Tcl), and hands-on experience with RTL2GDSII flows, synthesis, place-and-route and STA tools.
Apple in Cupertino, California, seeks a Senior ASIC Physical Design PPA Engineer to join the Digital Design Engineering group. You will partner with CAD, design, power and post-silicon teams to drive automation, scalability and reliability of PPA regression, delivering robust silicon for customers.
The role requires a BS and at least 3 years in the industry, strong scripting (Perl/Tcl), and hands-on experience with RTL2GDSII flows, synthesis, place-and-route and STA tools.