ASIC Physical Design Engineer Intern (Co-op)

Cisco; Maynard (MA); On-site; USD 18,000 - 30,000; Full time

Job summary

Cisco's Acacia PD team offers internship opportunities for ASIC physical design in Massachusetts. You will work on physical implementation tasks, including floorplanning, placement, CTS, routing, and optimization to meet power, performance and area goals.

Ideal candidates are undergraduates in CS/EE who will continue their degree and gain hands-on experience from RTL to GDSII, timing analysis, and signoff tooling. Opportunities arise as openings occur at Cisco.

Qualifications

• Currently enrolled in an undergraduate degree program (Associate's or Bachelor's).
• Qualifying education should be in Computer Science, Electrical Engineering, or related program.
• Expected to continue enrollment in degree program following completion of internship.
• Knowledge of the design cycle from RTL to GDSII.
• Understanding of Static Timing Analysis, timing closure and design constraints.
• Knowledge in block level synthesis, place and route, timing closure, PnR and signoff tools and their capabilities.

Responsibilities

• Work with Front-End teams to understand the design architecture to ensure optimal physical implementation
• Gate level netlist synthesis (physical synthesis)
• Physical implementation (floorplanning, placement, CTS, routing)
• Power, performance and area optimization of design
• Static Timing analysis and signoff closure
• Physical verification and signoff closure
• EMIR analysis and signoff closure

Skills

Analytical problem-solving

Scripting (Perl/Tcl/Python)

Strong communication

Education

Undergraduate degree in CS/EE or related

Tools

RTL to GDSII

Static Timing Analysis

Place & Route

Signoff tools

PnR tools

Job description

Cisco's Acacia PD team offers internship opportunities for ASIC physical design in Massachusetts. You will work on physical implementation tasks, including floorplanning, placement, CTS, routing, and optimization to meet power, performance and area goals.

Ideal candidates are undergraduates in CS/EE who will continue their degree and gain hands-on experience from RTL to GDSII, timing analysis, and signoff tooling. Opportunities arise as openings occur at Cisco.