SoC Physical Design Engineer — Power, P&R & Timing

Nokia; San Jose (CA); Ibrido; USD 140.000 - 210.000; Tempo pieno

Vantaggi offerti da questo lavoro

Flexible and hybrid working schemes

Maternity/Paternity leave (90 days)

Life insurance

Well-being programs

NERGs (Employee Resource Groups)

Career growth solutions

Coaches & mentors

Learning environment for growth

Descrizione del lavoro

Nokia is seeking an experienced ASIC physical design engineer to contribute to next-generation Optical Network ASICs. You will learn and apply advanced node flows, developing efficient implementation flows to optimize power, performance, and area.

You will collaborate with design and hardware teams, perform timing closure, and drive technology evaluations across 3/5/7nm nodes. A strong scripting background and hands-on P&R experience are essential for success.

Competenze

• Experience in ASIC physical design flow for 3/5/7nm nodes.
• Solid understanding of RTL to GDSII and submicron design concepts.
• Proficient in TCL/Python/Perl scripting for flow automation.

Mansioni

• Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level and full chip.
• Collaborate with logic designers and hardware teams to evaluate feasibility and trade-offs for physical design closure.
• Evaluate IP vendors, process nodes, and provide recommendations.
• Develop physical design methodologies and automation scripts from Synthesis to GDSII.
• Perform static timing analysis, create timing constraints, validate timing, and sign-off.

Conoscenze

ASIC physical design

Floor planning

Place & route

Timing closure

RTL to GDSII

Scripting (TCL/Python/Perl)

EDA tools (Fusion Compiler/Innovus)

Timing/PV tools (Primetime/Calibre)

IR/EM analysis

Formazione

Bachelor's degree in Electrical/Electronics/Communications/VLSI

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descrizione del lavoro

Nokia is seeking an experienced ASIC physical design engineer to contribute to next-generation Optical Network ASICs. You will learn and apply advanced node flows, developing efficient implementation flows to optimize power, performance, and area.

You will collaborate with design and hardware teams, perform timing closure, and drive technology evaluations across 3/5/7nm nodes. A strong scripting background and hands-on P&R experience are essential for success.