ASIC Physical Design Coop

NOKIA; San Jose (CA); Hybrid; USD 34,000 - 48,000; Full time

Job summary

Nokia of America is seeking an ASIC PD Coop in the NI ON Comp R&D ASICs & Architecture 4B group. You will analyze PPA metrics, build dashboards, and automate data tasks to support chip tape-outs in a Hybrid role based in San Jose, CA.

The candidate should be pursuing a Bachelor's or Master's in EE or CE and be comfortable collaborating across teams while learning new EDA/PNR workflows. The internship runs 4–8 months with start dates in Jan, May, or Aug 2027.

Qualifications

• Pursuing a Bachelor's or Master's in Electrical/Computer Engineering.
• Experience with data mining and visualization tools is preferred.
• Familiarity with ASIC design and physical design workflows is an asset.
• Strong problem-solving and analytical skills.
• Great communication and collaboration abilities.
• Ability to work independently and manage multiple tasks.
• Proficiency in Python or C++ is advantageous.
• Knowledge of EDA tools is a plus.
• Self-starter with proactive learning mindset.

Responsibilities

• Apply data mining and analytics to extract insights from PPA metrics and workflows.
• Develop and maintain PPA dashboards to visualize trends and opportunities.
• Automate data collection and analysis for internal PnR trials.
• Perform power estimation and analysis using data-driven methods.
• Conduct timing analysis with STA tools and correlate with PPA data.
• Collaborate with cross-functional teams to support physical design activities.
• Stay updated on industry trends to keep designs competitive.
• Document findings and communicate recommendations clearly.

Skills

Data analytics

Python

C++

Team collaboration

Education

Bachelor's or Master's in EE/CE

US accredited university

Tools

STA tools

EDA tools

Job description

At Nokia of America, we're seeking a talented and motivated ASIC PD Coop to join our NI ON Comp R&D ASICs & Architecture 4B department. In this role, you'll be an integral part of our Physical Design sub-group, supporting various tasks that contribute to the successful tape-out of Nokia's ASICs. Your work will focus on applying data mining and analytics techniques to extract valuable insights from PPA metrics and physical design workflows, helping us optimize our designs and stay at the forefront of technology.

Number of Positions: 1

Duration: 4-8 months

Dates: Jan - May - August 2027

Location: Hybrid in San Jose, CA

EDUCATIONAL RECOMMENDATIONS:

Currently a candidate pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with an accredited university in the USA.

• Apply data mining and analytics techniques to extract insights from PPA metrics and physical design workflows.
• Develop and maintain PPA dashboards to visualize trends and identify optimization opportunities.
• Automate data collection and analysis processes for internal Place-and-Route (PnR) trials, ensuring efficiency and accuracy.
• Perform power estimation and analysis using data-driven approaches, contributing to efficient design implementation.
• Conduct timing analysis using Static Timing Analysis (STA) tools and correlate results with PPA data for comprehensive design evaluation.
• Collaborate with cross-functional teams, providing support for physical design activities and troubleshooting issues.
• Stay updated with the latest industry trends and technologies, ensuring our designs remain competitive and innovative.
• Document and communicate your findings and recommendations effectively, ensuring a smooth workflow within the team.

• Strong academic background with a passion for data analytics and automation.
• Experience with data mining and visualization tools is preferred.
• Familiarity with ASIC design and physical design workflows is an asset.
• Excellent problem-solving and analytical skills, with a keen eye for detail.
• Strong communication and collaboration skills, able to work effectively in a team environment.
• Ability to work independently and manage multiple tasks simultaneously.
• Proficiency in programming languages such as Python or C++ is advantageous.
• Knowledge of EDA tools and design methodologies is a plus.
• A self-starter with a proactive approach to learning and adapting to new technologies.

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Our recruitment process

We act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.

If you're interested in this role but don't meet every listed requirement, we still encourage you to apply. Unique backgrounds, perspectives, and experiences enrich our teams, and you may be just the right candidate for this or another opportunity.

The length of the recruitment process may vary depending on the specific role's requirements. We strive to ensure a smooth and inclusive experience for all candidates. Discover more about the recruitment process at Nokia.