Senior SoC RTL Integration Lead

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA in Santa Clara, CA is seeking a Full-Chip RTL Integration Engineer to join the Advanced Technology Group. You will lead RTL integration of IPs into complex ASIC/SoC designs, owning clocking, reset, address mapping, and power domain integration while ensuring design quality and verification readiness.

Collaborate with Architecture, RTL Design, Verification, DFT and Physical Design teams, develop integration verification plans in SystemVerilog/UVM, and drive testability as well as

Qualifications

• 8+ years of experience in ASIC/SoC RTL integration.
• Strong knowledge of SystemVerilog and UVM for verification.
• Understanding of DFT methods including Scan, ATPG, MBIST, LBIST, JTAG.
• Experience with lint, CDC, RDC and design quality signoff flows.

Responsibilities

• Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs, owning top-level connectivity, clocking, reset architecture, address mapping, and power domain integration.

Skills

SystemVerilog

UVM

RTL integration

SoC architecture

DFT methods

Lint/CDC/RDC

Debugging

Python scripting

Shell scripting

Cross-team collaboration

Education

B.S. or M.S. in Electrical Engineering or Computer Engineering

Tools

Synopsys tools

Cadence tools

Siemens DFT tools

ATPg/MBIST/LBIST/JTAG tooling

Job description

NVIDIA in Santa Clara, CA is seeking a Full-Chip RTL Integration Engineer to join the Advanced Technology Group. You will lead RTL integration of IPs into complex ASIC/SoC designs, owning clocking, reset, address mapping, and power domain integration while ensuring design quality and verification readiness.

Collaborate with Architecture, RTL Design, Verification, DFT and Physical Design teams, develop integration verification plans in SystemVerilog/UVM, and drive testability as well as