Senior Logic Design Engineer, Cache Coherent Interconnects

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 265,000; Full time

Job summary

NVIDIA Corporation is seeking a Senior Logic Design Engineer to contribute to CPU on-chip and interconnect design, covering RTL, timing closure, and ASIC flow. You will collaborate with verification and implementation teams to meet timing and power goals, while mentoring juniors in a global, dynamic organization.

The role emphasizes deep hardware design expertise in CPU architecture, cache coherency, and high-speed interconnects, within NVIDIA's hybrid work environment.

Qualifications

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high performance semiconductor designs.
• Verilog expertise and deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

Responsibilities

• Write readable high performance and low power RTL, perform Synthesis and Timing closure, and document design.
• Collaborate with verification team to verify correctness of your unit.
• Work with implementation to achieve timing, area, performance and power goals.
• Assist with timing closure of super units.

Skills

Verilog

RTL design

ASIC design

Timing analysis

Education

Master's degree in Electrical/Computer Engineering or Computer Science

Job description

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. #LI-Hybrid

What you'll be doing:

As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip. Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation. Collaborate with our verification team to verify the correctness of your unit. Work with implementation to achieve your timing, area, performance and power goals. Assist with timing closure of super units.

What we need to see:

Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience. 5+ years of experience in processor or other related high performance semiconductor designs. Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Strong communication and interpersonal skills are required along with the work in a dynamic, global team. Your successful track record of mentoring junior engineers and interns a huge plus. A strong background in computer architecture, cache coherency or high speed interconnects is helpful.

Benefits and Compensation:

Your base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.

Application Deadline:

Applications for this job will be accepted at least until March 22, 2026.

Equal Opportunity Statement:

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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