ASIC Design Engineer: RTL & Microarchitecture, Equity

NVIDIA Corporation; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an ASIC Design Engineer in Santa Clara to build powerful SoC and GPU products. You will draft microarchitectures, implement RTL in Verilog, and drive verification across multiple IPs including GPU components.

The role requires 2+ years of RTL experience, strong Verilog skills, and proficiency in Perl/Python. You will collaborate with architects and verification teams to ensure high-performance, area- and power-efficient designs.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering or Computer Science.
• 2+ years of RTL design experience.
• Strong micro-architecture and RTL development (Verilog) with front-end flows (synthesis, power, timing).
• Exposure to Digital systems and VLSI design and computer architecture.

Responsibilities

• Draft microarchitecture documents and implement RTL that meets targets.
• Analyze architectural trade-offs for features, performance, and area/power constraints.
• Craft micro-architectures, implement in RTL, deliver fully verified builds.
• Collaborate with architects, designers, and verification teams to deliver RTL.
• Work on IPs including GPU time distribution, engine scheduler, interrupt controllers, and copy engines.
• Assist silicon bring-up and post-silicon validation.

Skills

Micro-architecture

RTL development

Verilog

Perl

Python

C/C++

Education

BS/MS in Electrical Engineering / Computer Engineering / Computer Science

Job description

NVIDIA is seeking an ASIC Design Engineer in Santa Clara to build powerful SoC and GPU products. You will draft microarchitectures, implement RTL in Verilog, and drive verification across multiple IPs including GPU components.

The role requires 2+ years of RTL experience, strong Verilog skills, and proficiency in Perl/Python. You will collaborate with architects and verification teams to ensure high-performance, area- and power-efficient designs.