Senior Circuit Timing Architect for AI-Driven SoCs

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA seeks a Senior Circuit Timing Engineer to join our advanced hardware team in Santa Clara. You will drive timing analysis and signoff for digital, semi-custom, and analog macros, leveraging Nanotime, PrimeTime, and Tempus while coordinating with PD, DFX, and Clocks groups.

The role emphasizes ECO-based timing fixes, low-power techniques, and an end-to-end silicon design flow from RTL to tape-out, with opportunities to apply AI/ML approaches during the design process.

Qualifications

• BSEE or MS preferred in Electrical/Computer Engineering or equivalent experience.
• 6+ years of digital circuit design experience for MS and 8+ years for BS.
• Excellent understanding of deep submicron process issues and digital circuit design techniques.
• Expertise with standard STA tools such as Nanotime, Primetime, Tempus, and SPICE tools.
• Hands-on experience with Spice simulations, EM/IR analysis, and static timing analysis/closure.
• Experience in timing constraints generation and management.
• Experience in low power circuits (power gating, decaps, multi-Vt) is a plus.
• Experience in ECOs to fix timing paths, including crosstalk and glitch noise.
• Knowledge of timing models and .libs usage in Primetime.
• Understanding of process variation and design convergence in multi-GHz tech.

Responsibilities

• Participate in groundbreaking processor design in deep submicron technologies.
• Design circuits for hardware security, adaptive clocking, and power management solutions.
• Drive timing analysis and signoff of custom circuit macros (digital, semi-custom and analog mixed-signal).
• Validate timing using STA tools (Nanotime, PrimeTime, Tempus) and SPICE simulations.
• Collaborate with cross-functional teams to improve power, performance, area and reliability of NVIDIA products.
• Develop timing models and methodology for custom macro designs.
• Transistor-level circuit design, timing, schematic entry, and layout delivery.
• Integrate AI/ML techniques into the design process and methodology.
• Coordinate with PD, DFX, Clocks, and other teams on timing signoff strategy and ECOs.

Skills

Digital circuit design

STA concepts

Spice simulations

Timing closure

Low power design

Education

BSEE

MS in Electrical/Computer Eng

Tools

Nanotime

Primetime

Tempus

SPICE

libs (.libs)

Job description

NVIDIA seeks a Senior Circuit Timing Engineer to join our advanced hardware team in Santa Clara. You will drive timing analysis and signoff for digital, semi-custom, and analog macros, leveraging Nanotime, PrimeTime, and Tempus while coordinating with PD, DFX, and Clocks groups.

The role emphasizes ECO-based timing fixes, low-power techniques, and an end-to-end silicon design flow from RTL to tape-out, with opportunities to apply AI/ML approaches during the design process.