ASIC Design Engineer – New College Grad 2026

Anysilicon; Santa Clara (CA); Hybrid; USD 90,000 - 130,000; Full time

Job summary

NVIDIA is seeking a Logic Design Engineer to join its CPU Logic Design Team in Santa Clara. You will own a unit on the chip, write high-performance RTL, and contribute to interconnect networks, caches, and timing closure.

The role requires a BS/MS in EE/CE/CS, experience in processor or high-performance designs, and a strong background in Verilog and ASIC design flow. Collaboration with verification and implementation teams is essential.

Qualifications

• Recent graduate with a BS or MS in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
• Experience in processor or high-performance semiconductor designs.

Responsibilities

• Own and deliver a specific unit on the chip in a timely manner.
• Write high-performance, low-power RTL code.
• Conduct synthesis and timing closure processes.
• Document design specifications and processes.
• Collaborate with the verification team to ensure unit correctness.
• Work with implementation teams to meet timing, area, performance, and power goals.
• Assist in timing closure of super units.

Skills

Verilog

ASIC design flow

RTL design

Timing analysis

DFT

Floor planning

Education

BS or MS in Electrical Engineering, Computer Engineering, or Computer Science

Job description

Job Description:

NVIDIA is seeking a Logic Design Engineer to join its CPU Logic Design Team, focusing on CPU on-chip interconnect networks, coherency, and last-level caches. This role involves micro-architectural definition, RTL coding, logic debug, synthesis, and timing closure, contributing to innovative product lines in consumer graphics, self-driving cars, and artificial intelligence.

Responsibilities

• Own and deliver a specific unit on the chip in a timely manner.
• Write high-performance, low-power RTL code.
• Conduct synthesis and timing closure processes.
• Document design specifications and processes.
• Collaborate with the verification team to ensure unit correctness.
• Work with implementation teams to meet timing, area, performance, and power goals.
• Assist in timing closure of super units.

Qualifications

• Recent graduate with a BS or MS in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
• Experience in processor or high-performance semiconductor designs.

Skills

• Expertise in Verilog and ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, and lab debug.
• Strong background in computer architecture, cache coherency, or high-speed interconnects.
• Effective communication and interpersonal skills.
• Experience mentoring junior engineers and interns is a plus.