Senior Logic Design Engineer – Cache Coherent Interconnects

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 265,000; Full time

Job summary

NVIDIA Corporation is seeking a Senior Logic Design Engineer to contribute to CPU on-chip and interconnect design, covering RTL, timing closure, and ASIC flow. You will collaborate with verification and implementation teams to meet timing and power goals, while mentoring juniors in a global, dynamic organization.

The role emphasizes deep hardware design expertise in CPU architecture, cache coherency, and high-speed interconnects, within NVIDIA's hybrid work environment.

Qualifications

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high performance semiconductor designs.
• Verilog expertise and deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

Responsibilities

• Write readable high performance and low power RTL, perform Synthesis and Timing closure, and document design.
• Collaborate with verification team to verify correctness of your unit.
• Work with implementation to achieve timing, area, performance and power goals.
• Assist with timing closure of super units.

Skills

Verilog

RTL design

ASIC design

Timing analysis

Education

Master's degree in Electrical/Computer Engineering or Computer Science

Job description

NVIDIA Corporation is seeking a Senior Logic Design Engineer to contribute to CPU on-chip and interconnect design, covering RTL, timing closure, and ASIC flow. You will collaborate with verification and implementation teams to meet timing and power goals, while mentoring juniors in a global, dynamic organization.

The role emphasizes deep hardware design expertise in CPU architecture, cache coherency, and high-speed interconnects, within NVIDIA's hybrid work environment.