ASIC Design Engineer — System-Level IP & RTL Expert

NVIDIA Corporation; Austin, Northern (TX, KY); Hybrid; USD 116,000 - 180,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Austin, TX is seeking an ASIC Design Engineer to drive system-level methodologies and RTL for measuring performance on leading GPUs and SOCs. You will define flows, automate IP delivery, and deliver IP while collaborating with architects, designers, and software engineers.

You will work on RTL checks (CDC, clocks, resets) and design implementation, improving methodologies and delivering system-level IP across projects in a fast-paced, innovative environment.

Qualifications

• BS or equivalent in Electrical/Computer Engineering or related field.
• 2+ years of industry experience in ASIC/SoC design.
• Experience in RTL design (Verilog) and verification (SystemVerilog).
• Understanding of SOC architecture, CDC, multi-power domains, and data flow.
• Strong debugging and analytical skills; good communication.

Responsibilities

• Define and deliver system-level methodologies and RTL for performance measurement.
• Develop flows to build, deliver, and support system-level IP.
• Run and debug RTL checks for design quality.
• Collaborate with architects, designers, and software engineers.

Skills

RTL design

Verilog

SystemVerilog

Python

Perl

CDC debugging

Cross-functional collaboration

Education

BS in Electrical/Computer Engineering

MS/PhD advantageous

Tools

dc_shell

VCS

Debussy

GDB

Job description

NVIDIA Corporation in Austin, TX is seeking an ASIC Design Engineer to drive system-level methodologies and RTL for measuring performance on leading GPUs and SOCs. You will define flows, automate IP delivery, and deliver IP while collaborating with architects, designers, and software engineers.

You will work on RTL checks (CDC, clocks, resets) and design implementation, improving methodologies and delivering system-level IP across projects in a fast-paced, innovative environment.