ASIC Design Verification Engineer [Remote]

Anysilicon; Chandler (AZ); Hybrid; USD 110,000 - 160,000; Full time

Job summary

Encore Semi, Inc. in Chandler, AZ is seeking a mid-level ASIC Verification Engineer to lead verification efforts for next-generation networking and AI accelerators.

This remote position is open to US Citizens or Lawful Permanent Residents and offers a competitive salary along with comprehensive benefits. The role requires building robust verification environments, planning test strategies, and mentoring junior engineers.

Qualifications

• 4+ years of ASIC/SoC verification experience with SystemVerilog and UVM.
• Experience in multi-clock and reset-domain designs.
• Bachelor’s in EE/CE/CS; Master’s preferred.
• Experience verifying high-speed networking tech (optional).

Responsibilities

• Lead end-to-end ASIC/SoC verification from planning through coverage and signoff.
• Build and enhance UVM/SystemVerilog verification environments at block, subsystem, and SoC levels.
• Create verification plans, develop test cases, execute regressions, and resolve RTL issues.
• Collaborate cross-functionally with ASIC design, hardware, and post-silicon teams to ensure first-pass silicon success.
• Mentor engineers, promote verification best practices, and utilize AI-driven tools to enhance productivity.

Skills

ASIC/SoC verification

UVM/SystemVerilog

Cross-functional collaboration

Mentoring and best practices

Scripting languages (Python Tcl Perl,

Education

Bachelor’s degree in electrical engineering, Computer Engineering, or Computer Science

Master’s degree preferred

Tools

VCS

Verdi

Git/SVN

Job description

Encore Semi, Inc., Chandler, AZ 85224 Remote

Job Description:

Encore Semi, Inc. is seeking a mid-level ASIC Verification Engineer to lead verification efforts for next-generation networking and AI accelerator SoCs. This remote position is open to US Citizens or Lawful Permanent Residents and offers a competitive salary along with comprehensive benefits.

Responsibilities:

• Lead end-to-end ASIC/SoC verification from planning through coverage and signoff.
• Build and enhance UVM/SystemVerilog verification environments at block, subsystem, and SoC levels.
• Create verification plans, develop test cases, execute regressions, and resolve RTL issues.
• Collaborate cross-functionally with ASIC design, hardware, and post-silicon teams to ensure first-pass silicon success.
• Mentor engineers, promote verification best practices, and utilize AI-driven tools to enhance productivity.

Qualifications:

• 4+ years of ASIC/SoC verification experience using SystemVerilog, UVM, VCS, and Verdi (or similar tools).
• Strong expertise in complex SoC verification, including multi-clock and reset-domain designs.
• Experience developing verification environments from the ground up.
• Knowledge of Git/SVN and scripting languages such as Python, Tcl, Perl, or Shell.
• Proven experience verifying high-speed networking technologies, including 50G/100G/400G Ethernet MAC/PCS, TCP/IP, UDP, RDMA/RoCE, or IPsec.
• Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related field (Master's preferred).

Skills:

• ASIC/SoC verification
• UVM/SystemVerilog
• Cross-functional collaboration
• Mentoring and best practices
• Scripting languages (Python, Tcl, Perl, Shell)