ASIC Verification engineer with Networking / Ethernet Verification

Tessolve; San Jose (CA); Teletrabalho; USD 150 000 - 200 000; Tempo integral

Resumo da oferta

Tessolve is seeking a senior ASIC Verification Engineer with Network/Ethernet expertise for San Jose, CA or REMOTE. The role emphasizes verification of Ethernet MAC/PHY, PCIe, TCP/IP, and related protocols within a full verification flow.

Candidates should have 10+ years of ASIC verification experience, strong SystemVerilog/UVM skills, and a proven ability to design modular, reusable testbenches and automated verification environments.

Qualificações

• BS or MS in Electrical Engineering, Computer Science, or related field.
• Minimum 10+ years of ASIC verification experience.
• Strong understanding of ASIC verification fundamentals and industry standard methodologies.
• Experience with Verilog/SystemVerilog, UVM, Python, TCL, C/C++.
• Experience with the full verification flow, from spec to coverage analysis to gate level sim.
• Debugging failures in simulation to root cause problems.
• Self-motivated and able to work effectively both independently and in a team.
• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other protocols).
• Digital signal processing filters and 3rd party IP (SerDes, controllers, processors, etc.).
• Modular and reusable testbench architecture.
• Design for re-use of pre and post silicon tests and infrastructure.
• Automation of testbench creation, tests, regression, or EDA tools.

Conhecimentos

Networking

Ethernet

TCP/IP

PCIe

Debugging

Testbench architecture

Formação académica

BS/MS in Electrical Engineering or Computer Science

Ferramentas

Verilog/SystemVerilog

UVM

Python

TCL

C/C++

Descrição da oferta de emprego

One of our valued customer is looking for ASIC Verification Engineer with Network / Ethernet Verification at San Jose, CA / REMOTE.

Here is the JD for your reference:

Network / Ethernet Verification Engineer

San Jose, CA / REMOTE

Key Qualifications:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC verification experience
• Strong understanding of ASIC verification fundamentals and industry standard methodologies
• Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
• Experience with the full verification flow, from spec to coverage analysis to gate level sim
• Debugging failures in simulation to root cause problems
• Self-motivated and able to work effectively both independently and in a team

Experience in any of the following areas:

Mandatory Experience:

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Digital signal processing filters
• Third party IP (SerDes, controllers, processors, etc.)
• Modular and Reusable Testbench architecture
• Design for re-use of pre and post silicon tests and infrastructure
• Automation of testbench creation, tests, regression, or EDA tools