ASIC Design Verification Emulation Engineer

Anysilicon; San Jose (CA); Hybrid; USD 170,000 - 230,000; Full time

Job summary

Cisco's Silicon One team in San Jose, CA is seeking an experienced verification leader to set vision and strategy for ASIC verification across multiple programs. You will mentor teams, lead architecture of scalable verification infrastructure, and drive cross-functional initiatives to improve coverage and quality.

Deep expertise in SystemVerilog/UVM and emulation is required. This role offers growth opportunities within a major tech company and local collaboration in a dynamic, innovative

Qualifications

• 7+ years in ASIC verification or related fields.
• Experience with verification methodologies and emulation.
• Leadership of verification teams or projects.

Responsibilities

• Set vision and strategy for ASIC verification across programs.
• Mentor verification teams and drive technical excellence.
• Lead scalable verification infrastructure and reusable methodologies.
• Drive cross-functional initiatives to improve verification efficiency, quality, and coverage at scale.
• Influence ASIC architecture and design to enable robust verification.
• Serve as subject matter expert on industry trends, best practices, and new technologies.
• Provide leadership in root cause analysis during bring-up and post-silicon validation.

Skills

Leadership

Communication

Mentoring

SoC verification

SystemVerilog/UVM

Python/Perl

Education

Bachelor's degree in EE/CS

Tools

SystemVerilog

UVM

Emulation tools

Python

C/C++

Job description

Join Cisco's Silicon One team in San Jose, CA, where you will play a pivotal role in developing a unified silicon architecture for web-scale and service provider networks. This position offers a unique blend of resources from a large organization and the dynamic culture of a smaller team, providing ample growth opportunities.

Responsibilities:

• Set vision and strategy for ASIC verification methodology and execution across multiple programs and product lines.
• Serve as technical authority and mentor for verification teams, fostering technical excellence and innovation.
• Lead architecture and implementation of scalable, reusable verification infrastructure and methodologies.
• Drive cross-functional initiatives to improve verification efficiency, quality, and coverage at scale.
• Influence ASIC architecture and design to enable robust verification and high-quality silicon.
• Serve as subject matter expert and advisor on industry trends, best practices, and new technologies.
• Provide technical leadership in root cause analysis and resolution of complex issues during bring-up and post-silicon validation.

Qualifications:

• Bachelor's degree with 7 years of related experience, or Master's degree with 4 years of related experience, or PhD with 1 year of related experience.
• Experience in System Verilog, UVM, and verification methodologies including emulation.
• Experience architecting verification strategies for complex ASIC programs.
• Experience leading verification teams or projects.
• Experience in scripting (Python, Perl) and C/C++ programming language.

Skills:

• Strong leadership, communication, and mentoring skills.
• Deep expertise in multiple protocols and large-scale SoC architectures.
• Experience with advanced emulation, prototyping, and formal verification tools at scale.
• Experience with silicon bring-up and post-silicon debug.