ASIC Engineer

Anysilicon; San Jose (CA); Hybrid; USD 180,000 - 250,000; Full time

Job summary

Cisco's Common Hardware Group is seeking an ASIC Design Verification Engineer to advance DV infrastructure and verification for state-of-the-art data center ASICs powering global networks.

You will architect and maintain DV environments, build block/cluster test benches, develop comprehensive test plans, and drive code and functional coverage, collaborating across design, architecture, and software teams to ensure smooth post-silicon bring-up and integration.

Qualifications

• Bachelor’s or higher in ECE or related field.
• Experience with ASIC verification required.
• Knowledge of SystemVerilog and UVM.

Responsibilities

• Architect, develop, and maintain DV environment infrastructure for block, cluster, and top-level designs.
• Build DV environments from scratch for block and cluster levels.
• Develop and enhance test plans and tests for block and cluster verification using constraint-random and directed stimulus.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.
• Qualify RTL design by running Gate Level Simulations on netlists.
• Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.

Skills

SystemVerilog & UVM

Constrained-random testing

Test benches from scratch

Python/Perl scripting

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree in Electrical/Computer Engineering

PhD in related field

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Join Cisco's Common Hardware Group (CHG) as an ASIC Design Verification Engineer, where you'll contribute to the development of cutting-edge data center solutions. Collaborate with a team dedicated to designing and testing advanced ASICs that power Cisco's core networking products for various sectors worldwide.

Responsibilities:

• Architect, develop, and maintain Design Verification (DV) environment infrastructure for block, cluster, and top-level designs.
• Build DV environments from scratch for block and cluster levels.
• Develop and enhance test plans and tests for block and cluster verification using constraint-random and directed stimulus.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.
• Qualify RTL design by running Gate Level Simulations on netlists.
• Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.

Qualifications:

• Bachelor’s degree + 5 years of ASIC experience, or Master’s degree + 3 years of ASIC experience, or PhD + 0 years of related experience.
• Experience in System Verilog and UVM methodology.
• Experience building reusable and scalable test benches from scratch.
• Experience with scripting using Perl and/or Python.

Skills:

• Experience with forwarding logic, parsers, or P4.
• Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Experience with formal verification tools (e.g., IEV or VC Formal).
• Familiarity with protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Work Email

Free • No obligation • Response within 24 hours