Senior ASIC Architect & Verification Lead - Onsite in San Jose

Cisco Systems, Inc.; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. is seeking an experienced ASIC verification engineer in San Jose to drive architecture, design, and verification of high-performance ASICs. You will own multiple functional areas, develop reusable code, and lead DV efforts across labs and platform reviews.

Candidates should have strong SystemVerilog, UVM, and debugging skills, plus exposure to emulation platforms (Veloce/Palladium/Zebu/HAPS), Linux/C/C++, and networking. On-site role with four days in San Jose.

Qualifications

• BS + 7 years experience or MS + 4 years or PhD + 2 years in related field.
• Experience with ASIC design and verification processes (SystemVerilog).
• Debugging, methodology, and tools experience.
• Experience leading verification methodology (UVM) of clusters/subsystems or full-chip level.

Responsibilities

• Drives definition, architecture and verification of high-performance ASICs.
• Owns complex or multiple functional areas.
• Develops reusable code for future projects and code reviews at platform level.
• Leads lab bring-up and power-saving solutions.
• Defines new verification methodologies and DV statistics.

Skills

ASIC design

SystemVerilog

DV statistics

UVM verification

emulation platforms

Linux/C/C++/Python

Networking

Education

Bachelor's degree +7 years

Master's degree +4 years

PhD +2 years

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Cisco Systems, Inc. is seeking an experienced ASIC verification engineer in San Jose to drive architecture, design, and verification of high-performance ASICs. You will own multiple functional areas, develop reusable code, and lead DV efforts across labs and platform reviews.

Candidates should have strong SystemVerilog, UVM, and debugging skills, plus exposure to emulation platforms (Veloce/Palladium/Zebu/HAPS), Linux/C/C++, and networking. On-site role with four days in San Jose.