ASIC Engineering Technical Leader

Anysilicon; North Carolina; Hybrid; USD 180,000 - 240,000; Full time

Job summary

Cisco Systems in RTP, NC is seeking an ASIC Technical Lead to drive front-end ASIC development, architecture, verification, synthesis, and timing analysis for high-performance networks.

You will mentor engineers, review designs, develop RTL subsystems, create clocking diagrams, and collaborate with Physical Design, DFT, SW/SDK teams to deliver a unified silicon architecture across web-scale and service-provider networks.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering with required years of ASIC experience.
• Experience in block/subsystem RTL development and STA.
• Proficient with PrimeTime/Tempus and synthesis tools.
• Strong Verilog/SystemVerilog and HDL skills.

Responsibilities

• Lead front-end ASIC development including architecture, design, verification, synthesis, and STA.
• Review specs and participate in design reviews to influence testability and verification efficiency.
• Architect RTL subsystems and perform top-level IP integration.
• Mentor early-career engineers and foster continuous improvement.
• Collaborate with Physical Design and DFT teams to meet timing and testability.
• Partner with SW/SDK teams to implement system-level features and APIs.

Skills

Frontend ASIC development

RTL design

Static Timing Analysis

Verilog/SystemVerilog

Design Verification

Clocking and timing

Scripting (Python, TCL)

Mentorship

Education

Electrical or Computer Eng degree

Tools

PrimeTime/Tempus

Synopsys DC/DCG/FC

Verilog/SystemVerilog

Veloce/HAPS

Spyglass & Cadence LEC

Job description

Cisco Systems, Research Triangle Park, NC

Job Description:

Join the Cisco Silicon One team as an ASIC Technical Lead, where you will contribute to the development of a unified silicon architecture for web scale and service provider networks. This role combines the resources of a large organization with the dynamic culture of a smaller team, offering unique growth opportunities.

Responsibilities:

• Lead front-end ASIC development initiatives including Architecture, Design, Design Verification, Synthesis, and Static Timing Analysis.
• Review specifications and participate in design reviews to influence architecture for testability and verification efficiency.
• Architect and design RTL subsystems and perform top-level IP integration.
• Mentor early-career engineers in front-end ASIC development, fostering continuous improvement in technical skills.
• Perform Synthesis and Timing analysis, including the development of SDCs.
• Collaborate with Physical Design teams to verify timing and ensure manufacturability.
• Work with DFT teams to meet testability requirements.
• Debug complex silicon and system-level issues during emulation and bring-up.
• Conduct Post Silicon Validation and assess performance vs power trade-offs.
• Collaborate with SW/SDK teams to implement necessary system-level features and APIs.
• Create full-chip clocking diagrams and related documentation.

Qualifications:

• Bachelor’s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master’s degree with 6+ years of experience.
• Experience with block/subsystem RTL development.
• Experience in Static Timing Analysis and familiarity with STA tools like PrimeTime/Tempus.
• Experience with synthesis tools (e.g., Synopsys DC/DCG/FC) and Verilog/System Verilog programming.

Skills:

• Influencing design for testability and verification.
• Power savings techniques including clock gating and multi-voltage domains.
• Experience with Spyglass CDC and glitch analysis.
• Emulation and prototyping platforms (Veloce, HAPS).
• Formal Verification tools like Synopsys Formality and Cadence LEC.
• Expertise in protocols such as PCIe, CXL, Ethernet, AXI, DDR, MMU.
• Scripting languages such as Python, Perl, or TCL.