ASIC Design Engineer Intern

Meta; Sunnyvale (CA); On-site; USD 55,000 - 83,000; Full time

Job summary

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. You will help design and verify advanced IPs for data center workloads, contributing to accelerators for scalable services.

The internship offers hands-on experience in HDL/verification and collaboration with expert ASIC engineers. The 12-week program targets students pursuing Bachelor's, Masters, or PhD in Electrical/Computer Engineering with knowledge of Verilog/SystemVerilog and HPC concepts, and a passion

Qualifications

• Pursuing or holds a degree in Electrical or Computer Engineering or related field.
• Experience with HDL and design verification concepts preferred.
• Knowledge of computer architecture and digital design fundamentals required.

Responsibilities

• Contribute to design and verification of advanced IPs for data center workloads.
• Collaborate with ASIC engineers to build green data center accelerators.
• Participate in design/verification using state-of-the-art tools during a 12-week internship.

Skills

Verilog/SystemVerilog/HLS

Computer Architecture

Python/Perl scripting

High Performance Computing

Digital Signal Processing

Creative problem solving

Education

Bachelors in Electrical/Computer Engineering

Masters/PhD in Electrical/Computer Engineering

Tools

Lint/Synthesis/ Formal or Physical Design tools

Job description

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design and verification of advanced IPs using state of the art tools. Come work and learn alongside our expert ASIC engineers to build Green data center accelerators.

This is a 12 week internship.

• Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
• Knowledge of Verilog or System Verilog or HLS
• Knowledge of Computer Architecture and Logic Design fundamentals
• Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
• Intent to return to full-time degree program after completion of the internship
• Currently has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields
• Experience with Lint, Synthesis, Formal or Physical Design tools
• Scripting capability with Python or Perl
• Experience with High Performance Computing
• Experience with Digital Signal Processing Techniques
• Creativity and problem solving capabilities