ASIC Design-for-Test (DFT) Engineer Intern

Keysight Technologies SAles Spain SL.; Colorado Springs (CO); On-site; USD 45,000 - 59,000; Part time

Job summary

Keysight Technologies in Colorado Springs offers an ASIC Design-for-Test (DFT) Engineer Intern role within its ASIC R&D organization. You will gain hands-on experience with DFT methodologies, scan insertion, ATPG, MBIST, and scripting to improve workflows.

Collaborating with design, verification, and test engineers, you will contribute to silicon bring-up and production test development, using tools like Siemens Tessent and other industry flows, while pursuing a degree in EE/CE/CS.

Qualifications

• Pursuing Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science or related field.
• Sophomore year completed by Summer 2027 or later.
• Coursework in Digital Logic Design, Computer Architecture, VLSI Design, FPGA Design.
• Understanding of digital circuits, finite state machines, and hardware fundamentals.
• Programming or scripting in Python, C/C++, Tcl, Ruby, or similar.
• Strong analytical, problem-solving and debugging skills.
• Team-oriented and collaborative work style.

Responsibilities

• Support development and verification of DFT architectures for complex digital and mixed-signal ASICs.
• Learn and apply industry-standard DFT methodologies (scan insertion, scan compression, ATPG, MBIST).
• Assist ATPG pattern generation, coverage analysis, and debug using industry tools.
• Develop scripts to improve engineering workflows and data analysis.
• Collaborate with design, verification, physical design, and product engineering teams.
• Participate in silicon bring-up, characterization, and failure analysis activities.
• Analyze test results and help improve test quality and efficiency.

Skills

Python

C/C++

Tcl

Ruby

Strong analytical skills

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Job description

Overview

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~16,800 employees create world‑class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award‑winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry‑first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

Job Description

Keysight Technologies has an exciting opportunity for an ASIC Design‑for‑Test (DFT) Engineer Intern within our ASIC R&D organization. This role provides hands‑on experience across the semiconductor product development lifecycle, with a focus on Design‑for‑Test (DFT) methodologies used to ensure the manufacturability, quality, and reliability of advanced integrated circuits.

Working alongside experienced ASIC Test Engineers, you will gain exposure to industry‑standard EDA tools and flows used for scan insertion, ATPG pattern generation, memory test, silicon validation, and production test development. This internship is an excellent opportunity for students interested in digital design, VLSI, semiconductor development, and hardware engineering to gain practical experience on real ASIC programs.

As an intern, you will collaborate with ASIC design, verification, physical design, and test engineers while contributing to projects that directly impact the successful development and release of next‑generation semiconductor products.

This position is based in Colorado Springs, Colorado, consistently recognized as one of the nation's most desirable places to live.

Responsibilities

• Support the development and verification of DFT architectures for complex digital and mixed‑signal ASICs
• Learn and apply industry‑standard DFT methodologies, including scan insertion, scan compression, ATPG, Streaming Scan Networks, and memory BIST (MBIST)
• Assist with ATPG pattern generation, coverage analysis, and debug using Siemens Tessent and other industry‑standard EDA tools
• Develop scripts and automation solutions using Python, Ruby, Tcl, or similar languages to improve engineering workflows and data analysis
• Collaborate with ASIC design, verification, physical design, and product engineering teams to ensure testability requirements are incorporated throughout the design lifecycle
• Participate in silicon bring‑up, characterization, debug, and failure analysis activities
• Analyze test results and help develop solutions to improve test quality, coverage, and efficiency

Basic Qualifications

• Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
• Completion of sophomore year or higher by Summer 2027
• Coursework in Digital Logic Design, Computer Architecture, VLSI Design, FPGA Design, or related areas
• Understanding of digital circuits, finite state machines, and computer hardware fundamentals
• Programming or scripting experience in Python, C/C++, Tcl, Ruby, or similar languages
• Strong analytical, problem‑solving, and debugging skills
• Demonstrated ability to work effectively in a collaborative team environment

Desired Qualifications

• Strong Interest in semiconductor design, ASIC development, hardware verification, or Design‑for‑Test (DFT) methodologies
• Familiarity with Verilog, SystemVerilog, or VHDL
• Knowledge of Linux/Unix environments and scripting
• Exposure to ASIC design flows, RTL development, simulation, or verification
• Familiarity with DFT concepts such as scan chains, ATPG, boundary scan, test compression, or memory BIST
• Exposure to EDA tools such as Siemens Tessent, Synopsys TestMAX, Cadence Modus, or similar tools
• Strong written and verbal communication skills
• Demonstrated ability to work independently while managing multiple technical tasks and priorities

CO Pay Range

Bachelors- $33.28-$35.83

Masters-$40.06-43.14

Note: For other locations, pay ranges will vary by region.

Based on experience, education and skills, most offers will be between the minimum and the midpoint of the Salary Range listed above.

Candidates who wish to be considered must be enrolled in a accredited college/university as of September 2027. Applicants who have graduated before September 2027 will not be considered unless they are starting a MS or PHD program after graduating.

Visa Sponsorship is not available for this position. Candidates who now or at any point in the future require sponsorship for employment visa status (e.g., H-1B Visa status) may not be considered.

Careers Privacy Statement

Keysight is an Equal Opportunity Employer.

Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.