ASIC Engineer I, Annapurna Labs, Early Career – 2027

Anysilicon; Austin (TX); Hybride; USD 41 000 - 69 000; Plein temps

Résumé du poste

Amazon is seeking an ASIC Engineer I intern to design and implement RTL for digital logic blocks and collaborate with cross-functional teams in a fast-paced environment.

You will gain hands-on experience in verification, synthesis, timing analysis, and physical design flows while contributing to silicon-ready features for global services.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, graduating by May 2027 or earlier.
• Coursework or project experience in digital logic design and computer architecture.
• Familiarity with a hardware description language (Verilog, SystemVerilog, or VHDL).

Responsabilités

• Design and implement RTL for digital logic blocks using Verilog/SystemVerilog.
• Develop and run verification environments to validate design functionality and coverage.
• Support synthesis, timing analysis, and physical design flows.
• Debug design issues through simulation and analysis.
• Collaborate with architecture, verification, and physical design teams to transition features from specification to silicon.
• Document design decisions and present work to the team.

Connaissances

EDA tools

Scripting

Hardware development

Internship/lab experience

Formation

Bachelors/Masters in EE/CE/CS

Outils

Verilog

SystemVerilog

VHDL

Description du poste

Job Description:

Join Amazon as an ASIC Engineer I, where you'll work on cutting-edge custom silicon technologies that power our global services. This internship offers hands-on experience in designing and implementing digital logic for products that impact millions of customers. You'll collaborate with diverse teams, take ownership of projects, and develop your skills in a dynamic environment.

Responsibilities:

• Design and implement RTL for digital logic blocks using Verilog/SystemVerilog.
• Develop and run verification environments to validate design functionality and coverage.
• Support synthesis, timing analysis, and physical design flows.
• Debug design issues through simulation and analysis.
• Collaborate with architecture, verification, and physical design teams to transition features from specification to silicon.
• Document design decisions and present work to the team.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, graduating by May 2027 or earlier.
• Coursework or project experience in digital logic design and computer architecture.
• Familiarity with a hardware description language (Verilog, SystemVerilog, or VHDL).
• Understanding of fundamental digital design concepts: combinational and sequential logic, finite state machines, timing, and clocking.

Skills:

• Experience with industry-standard EDA tools (Cadence, Synopsys, or equivalent).
• Scripting experience (Python, Perl, TCL, or shell) for automation and design flows.
• Prior internship, research, or lab experience in chip design, embedded systems, or hardware development.