2027 Summer Intern - Design Verification

ForwardEdge ASIC LLC; Saint Paul (MN); On-site; USD 25,000 - 39,000; Full time

Benefits offered by this job

Mentorship

Hands-on project experience

Competitive compensation

Job summary

ForwardEdge ASIC LLC in Saint Paul, MN is seeking an ASIC Design Verification Engineer Intern to support verification of ASIC and FPGA designs. You will work under experienced engineers to build verification environments and run tests.

Candidates pursuing a degree in electrical or computer engineering, with strong VLSI and digital logic coursework, and programming skills in Python or similar languages, are encouraged to apply. U.S. citizenship is required.

Qualifications

• Pursuing a bachelor’s or master’s degree in electrical or computer engineering.
• Strong coursework in VLSI design and digital logic.
• Proficiency in Python or similar object-oriented languages.
• Excellent communication and teamwork in a fast-paced environment.
• US citizenship is required.

Responsibilities

• Verify ASIC and FPGA designs across products.
• Create verification environments using SystemVerilog.
• Understand block-to-top UVM constrained random environments.
• Apply functional coverage, assertions, debug and formal verification.
• Collaborate with digital design engineers to ensure coverage.
• Automate processes with scripting (Python, Perl, TCL).

Skills

SystemVerilog

Python

Digital logic

VLSI design

Communication

Teamwork

US citizenship

Education

Bachelor's or Master's in Electrical/Computer Engineering

Job description

Position Description:

At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design.

As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents.

Position Summary

As an ASIC Design Verification Engineer Intern, you will be verifying ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products. Your responsibility will include all aspects of ASIC verification. You will benefit from the experience of a highly qualified ASIC team.

Responsibilities include, but are not limited to the following:

• Working under the direction of experienced verification engineers to understand how to verify the functions and requirements for design blocks.
• Creating verification environments utilizing industry standard verification languages including, but not limited to SystemVerilog.
• Understanding block-to-top UVM constrained random environments.
• Utilizing best practices methodology for functional coverage, assertions, debug and formal verification.
• Working closely with the digital design engineers to ensure comprehensive functional and code coverage metrics.
• Process and methodology automation utilizing common scripting languages (i.e. python, perl, tcl).

Qualifications

• Actively working toward a bachelor’s or master’s degree in electrical engineering or computer engineering
• Strong course work in VLSI design, digital logic
• Proficiency or intermediate level Programming skills such as Python or other object-oriented languages
• Strong analytical and problem‑solving skills with attention to detail
• Excellent communication and teamwork skills; ability to work in a fast-paced engineering environment
• US citizenship

Join ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world.