Digital Design Engineer (New Grad / Entry-Level) – ASIC Design Services

VeriSilicon Holdings Co., Ltd.; San Jose (CA); On-site; USD 90,000 - 130,000; Full time

Job summary

VeriSilicon Holdings Co., Ltd. seeks highly motivated New Grad Digital Front-End Design Engineers to join our ASIC Design Services team in the United States.

You will independently contribute to RTL design, functional verification, logic synthesis, timing analysis, DFT insertion, and test pattern generation while collaborating with system engineers, physical design, DFT, and ATE/test engineers to deliver high-quality silicon.

Qualifications

• Master’s or above degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Recent graduate or graduating within the last 12 months (New Grad / Entry-Level).
• Strong academic background or project experience in ASIC design, digital front-end design, RTL design, and verification.
• Familiar with RTL coding and UVM (Verilog/SystemVerilog).
• Familiar with the ASIC design flow, including specification, architecture definition, RTL coding, verification, and synthesis.
• Adept at EDA tools (Synopsys or Cadence), such as VCS, Xcelium, DC, PT, etc.
• Familiar with C/C++, Perl, Python, or other programming languages.
• Knowledge of SOC on-chip bus protocols (AMBA/NOC) is a plus.
• Knowledge of processor design (ARM or RISC-V) is a plus.
• Knowledge of interfaces such as USB/PCIe/CXL/UCIe/Ethernet/DDR/UFS/DP is a plus.
• Familiar with usage of AI Agent is a plus.
• Self-motivated and a good team player.
• Good communication skills in both Chinese and English in either listening, speaking, reading, or writing.

Responsibilities

• Independently work on the design of ASIC functional blocks in terms of requirement analysis, architecture definition, RTL coding, block design, logic synthesis, and timing analysis (STA).
• Independently work on the verification of ASIC functional blocks in terms of verification plan, test bench building, test case development, simulation, and debugging.
• Perform logic synthesis and timing analysis of chips and sub-blocks.
• Perform DFT RTL coding, scan chain/MBIST/boundary scan circuit insertion, and test pattern generation and simulation.
• Work closely with system engineers, physical implementation designers, DFT engineers, and testing engineers to complete functional verification, floorplan design, timing optimization/closure, and DFT & ATE testing.
• Support multiple customer projects simultaneously in a fast-paced design services environment.
• Participate in design reviews, documentation, and customer technical discussions.
• Continuously improve design/verification methodologies and flow automation.

Skills

ASIC design

digital front-end design

RTL design

verification

C/C++

Python

Verilog/SystemVerilog

UVM

VCS/Xcelium/DC/PT

AMBA/NOC knowledge

ARM/RISC-V knowledge

Education

Master's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

VCS

Xcelium

DC

PT

Git

Linux

Job description

We are seeking highly motivated New Grad Digital Front-End Design Engineers to join our ASIC Design Services team in the United States. In this role, you will work on challenging customer projects across a wide range of applications, including SoC, AI accelerators, networking, storage, automotive, and high-performance computing.

As part of a world-class design services organization, you will independently contribute to RTL design, functional verification, logic synthesis, timing analysis, DFT insertion, and test pattern generation, while collaborating closely with system engineers, physical design engineers, DFT engineers, and ATE/test engineers to deliver high-quality silicon.

This is an excellent opportunity for a recent Master’s graduate in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a strong background in ASIC design, digital front-end design, and verification to grow rapidly in a multi-project, customer-facing environment.

Responsibilities

• Independently work on the design of ASIC functional blocks in terms of requirement analysis, architecture definition, RTL coding, block design, logic synthesis, and timing analysis (STA).
• Independently work on the verification of ASIC functional blocks in terms of verification plan, test bench building, test case development, simulation, and debugging.
• Perform logic synthesis and timing analysis of chips and sub-blocks.
• Perform DFT RTL coding, scan chain/MBIST/boundary scan circuit insertion, and test pattern generation and simulation.
• Work closely with system engineers, physical implementation designers, DFT engineers, and testing engineers to complete functional verification, floorplan design, timing optimization/closure, and DFT & ATE testing.
• Support multiple customer projects simultaneously in a fast-paced design services environment.
• Participate in design reviews, documentation, and customer technical discussions.
• Continuously improve design/verification methodologies and flow automation.

Requirements

• Master’s or above degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Recent graduate or graduating within the last 12 months (New Grad / Entry-Level).
• Strong academic background or project experience in ASIC design, digital front-end design, RTL design, and verification.
• Familiar with RTL coding and UVM (Verilog/SystemVerilog).
• Familiar with the ASIC design flow, including specification, architecture definition, RTL coding, verification, and synthesis.
• Adept at EDA tools (Synopsys or Cadence), such as VCS, Xcelium, DC, PT, etc.
• Familiar with C/C++, Perl, Python, or other programming languages.
• Knowledge of SOC on-chip bus protocols (AMBA/NOC) is a plus.
• Knowledge of processor design (ARM or RISC-V) is a plus.
• Knowledge of interfaces such as USB/PCIe/CXL/UCIe/Ethernet/DDR/UFS/DP is a plus.
• Familiar with usage of AI Agent is a plus.
• Self-motivated and a good team player.
• Good communication skills in both Chinese and English in either listening, speaking, reading, or writing.

Preferred Qualifications

• Hands-on internship or co-op experience in ASIC design, digital front-end design, verification, or DFT.
• Experience with scripting and flow automation (Python, Perl, Tcl, Makefile).
• Familiarity with Git, Linux, and regression environments.
• Exposure to low-power design techniques (UPF/CPF) is a plus.
• Exposure to formal verification, CDC/RDC, or lint is a plus.
• Knowledge of AI/ML accelerators, high-speed interfaces, or compute SoCs is a plus.
• Strong publication, tapeout, or chip design project experience is a plus.