Sr. ASIC/FPGA Design Engineer

Mavensoft Technologies, LLC; United States; Remote; CAD 124,000 - 207,000; Full time

Job summary

Mavensoft Technologies, LLC is seeking a Sr. ASIC/FPGA Design Engineer for a fully remote, 8-month W2 contract.

The role focuses on designing digital ASICs and FPGAs, with HDL proficiency across VHDL/Verilog/SystemVerilog, and requires strong verification and lab-support capabilities. You will collaborate with systems, firmware, architecture, and product engineering teams to address timing, congestion, and implementation challenges, while developing test plans, coverage models, and signoff

Qualifications

• 7+ years of experience in ASIC design and implementation.
• Experience with FPGA & ASIC design.
• Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog).
• Experience with Linux development environment.
• Experience with design verification and test bench development.

Responsibilities

• Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs. Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog).
• Develop verification methodologies and test benches for block and system-level verification.
• Create and execute test plans, develop test harnesses, and implement coverage models.
• Conduct timing analysis, noise analysis, and other signoff checks.
• Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.
• Support lab integration and troubleshooting activities.
• Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.

Skills

FPGA & ASIC design

Verilog

VHDL

SystemVerilog

Linux development

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

RTL2GDSII flows

EDA tools

Linux tooling

Job description

Job Title: Sr. ASIC/FPGA Design Engineer

Work Location: Fully remote

Duration: 8 months

Terms: W2 Contract

Key Skills: FPGA and Application-Specific Integrated Circuit (ASIC), Verilog, VHDL, SystemVerilog

Responsibilities:

• Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog).
• Develop verification methodologies and test benches for block and system-level verification.
• Create and execute test plans, develop test harnesses, and implement coverage models.
• Conduct timing analysis, noise analysis, and other signoff checks.
• Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.
• Support lab integration and troubleshooting activities.
• Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.

Required Qualifications:

• 7+ years of experience in ASIC design and implementation.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Experience with FPGA & ASIC design.
• Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog).
• Experience with Linux development environment.
• Experience with design verification and test bench development.

Preferred Qualifications:

• Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field.
• Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test).
• Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs.
• Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM).
• Strong object-oriented programming and scripting skills (Python, TCL, Perl).
• Experience with physical design flows and industry-standard EDA tools.
• Experience with RTL2GDSII physical design and signoff flows.
• Knowledge of deep sub-micron FinFET and CMOS technologies.
• Experience with DFT/Scan/MBIST/LBIST methodologies.
• Experience mentoring junior engineers.

Authorized US Worker - US Citizens and those authorized to work in the US are encouraged to apply. We are unable to sponsor at this time.