ASIC Design Engineer Intern: Green Data Center Accelerators

Meta; Sunnyvale (CA); On-site; USD 55,000 - 83,000; Full time

Job summary

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. You will help design and verify advanced IPs for data center workloads, contributing to accelerators for scalable services.

The internship offers hands-on experience in HDL/verification and collaboration with expert ASIC engineers. The 12-week program targets students pursuing Bachelor's, Masters, or PhD in Electrical/Computer Engineering with knowledge of Verilog/SystemVerilog and HPC concepts, and a passion

Qualifications

• Pursuing or holds a degree in Electrical or Computer Engineering or related field.
• Experience with HDL and design verification concepts preferred.
• Knowledge of computer architecture and digital design fundamentals required.

Responsibilities

• Contribute to design and verification of advanced IPs for data center workloads.
• Collaborate with ASIC engineers to build green data center accelerators.
• Participate in design/verification using state-of-the-art tools during a 12-week internship.

Skills

Verilog/SystemVerilog/HLS

Computer Architecture

Python/Perl scripting

High Performance Computing

Digital Signal Processing

Creative problem solving

Education

Bachelors in Electrical/Computer Engineering

Masters/PhD in Electrical/Computer Engineering

Tools

Lint/Synthesis/ Formal or Physical Design tools

Job description

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. You will help design and verify advanced IPs for data center workloads, contributing to accelerators for scalable services.

The internship offers hands-on experience in HDL/verification and collaboration with expert ASIC engineers. The 12-week program targets students pursuing Bachelor's, Masters, or PhD in Electrical/Computer Engineering with knowledge of Verilog/SystemVerilog and HPC concepts, and a passion