Application Engineer Architect (STA SignOff)

Cadence Design Systems; United States; Vor Ort; USD 154.000 - 286.000; Vollzeit

Benefits dieser Stelle

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision plan

Zusammenfassung

Cadence Design Systems seeks a senior leader to drive customer engagements and adoption of our timing signoff portfolio. You will collaborate with design teams to meet success metrics on advanced nodes (5nm and below) and influence tool enhancements through close partnership with R&D and Product Engineering.

The role demands strong scripting skills and proven multi-team leadership. Based in the United States, this position offers exposure to cutting-edge signoff methodologies, industry forums,

Qualifikationen

• 15+ years of experience in IC design implementation and signoff.
• Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below).
• Core timing signoff expertise and constraints debugging.
• Proven track record leading technical teams and driving customer success at executive levels.
• Strong scripting skills (Tcl, Python, Perl) and flow customization for design closure.

Aufgaben

• Lead technical engagements with customers and partners to drive adoption of Cadence signoff portfolio.
• Collaborate with design teams to meet customer success metrics and guide adoption across advanced nodes.
• Influence tool enhancements with R&D and Product Engineering based on customer requirements.
• Drive benchmarks, flow optimizations, and deployment of methodologies for timing signoff, STA, IR Drop, power/timing closure.
• Represent Cadence at industry forums, author technical papers, and deliver keynote presentations.

Kenntnisse

Tcl

Python

Perl

Ausbildung

B.S. in Electrical Engineering

M.S. in Electrical/Computer Engineering

Tools

Tempus

Certus

QRC

Jobbeschreibung

Key Responsibilities

• Lead technical engagements with customers and partners to drive & adoption of Cadence signoff portfolio.
• Work closely with design teams to meet customer success metrics, guide adoption of Cadence’s timing signoff & closure and AgenticAI features across advanced nodes (5nm and below).
• Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
• Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing sigoff & closure, STA, IR Drop, and power/timing closure.
• Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Qualifications

• 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems.
• Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions.
• Proven track record of leading technical teams and driving customer success at executive levels.
• Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
• Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
• Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable.

Salary

The annual salary range for Washington is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.

Benefits

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options
• and more

About the Company

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Equal Employment Opportunity

We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

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