Analog Design Engineer – FinFET PLLs & VCOs

TekWissen ®; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

TekWissen® Group is seeking an experienced Analog Circuit Design Engineer to work on FinFET-based PLLs and related blocks in a fast-paced semiconductor environment. The role requires hands-on design, verification flows, and close collaboration with layout and test teams to ensure robust, high-yield silicon.

You will design PLL building blocks, run pre-tapeout verifications, and help define production test plans with post-silicon characterization groups. 3–5 years of relevant experience preferred.

Qualifications

• Solid knowledge Analog Circuit Design in FinFET technology, PLLs and subblocks.
• Good knowledge in Physical design, STA, scripting (Tcl), Perl, Python.
• Quality-oriented mindset and strong communication.
• 3–5 years of professional semiconductor experience.

Responsibilities

• Help design building blocks of a PLL.
• Run pre-tapeout verification to confirm performance, power, reliability and timing.
• Work with layout to deliver the physical design and define production/test plans with post-silicon characterization groups.

Skills

Analog Circuit Design

FinFET Technology

Cadence ADE-L/ADE-XL

Scripting (Python, Perl)

Physical Design & STA

Team Collaboration

Education

Master's or Bachelor's degree in Electrical Engineering

Tools

Cadence Tools (ADE-L/ADE-XL)

Spectre/HSPICE

MATLAB

SystemVerilog

Calibre/ICV (layout verification)

Job description

TekWissen® Group is seeking an experienced Analog Circuit Design Engineer to work on FinFET-based PLLs and related blocks in a fast-paced semiconductor environment. The role requires hands-on design, verification flows, and close collaboration with layout and test teams to ensure robust, high-yield silicon.

You will design PLL building blocks, run pre-tapeout verifications, and help define production test plans with post-silicon characterization groups. 3–5 years of relevant experience preferred.