Senior Analog & Mixed-Signal PLL Designer

Samsung-Semiconductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

Charitable giving match

Paid time off 4+ weeks

Fertility/adoption support

Mental health resources

Onsite gym & cafe

Flexible work environment

Job summary

Samsung Semiconductor, Inc. is seeking a talented Senior/Staff PLL Designer to develop high‑performance PLL and clocking subsystems for RF transceivers, SerDes, and high‑speed I/O.

You will design and verify frequency synthesizers and clock generation circuitry in advanced CMOS tech. The role requires extensive hands‑on experience with VCOs, DCOs, phase detectors, and related circuitry, plus strong CAD tool proficiency and layout skills.

Qualifications

• Bachelor’s degree in a related field with extensive experience
• Hands-on experience in designing frequency synthesizers and clock generation circuits in deep sub-micron CMOS
• Ability to comprehend PLL loop system knowledge to circuit level specifications
• Strong knowledge of IC design CAD tools such as Spectre, SpectreRF, AMS simulator, Matlab
• Understanding physical layout requirements and ability to perform critical layouts
• Lab testing skills to evaluate prototype units to design specs
• Motivated to carry out a wide variety of tasks with clear communication in a dynamic team

Responsibilities

• Design RF/Analog PLL and clocking circuits in deep sub-micron CMOS technologies
• Design Serdes analog PHY circuits in deep sub-micron CMOS technologies
• Perform system modeling and analysis for mixed signal system
• Perform design verification and production support tasks
• Collaborate with digital and software teams to meet system requirements

Skills

PLL design

Clock generation

VCO

DCO

Phase detector

IC design CAD tools

Layout knowledge

Lab testing

Team collaboration

Education

Bachelor’s degree in related field

Master’s degree in related field

PhD in related field

Tools

Spectre

SpectreRF

AMS simulator

Matlab

Job description

Samsung Semiconductor, Inc. is seeking a talented Senior/Staff PLL Designer to develop high‑performance PLL and clocking subsystems for RF transceivers, SerDes, and high‑speed I/O.

You will design and verify frequency synthesizers and clock generation circuitry in advanced CMOS tech. The role requires extensive hands‑on experience with VCOs, DCOs, phase detectors, and related circuitry, plus strong CAD tool proficiency and layout skills.