Senior Analog & RF IC Layout Engineer – FinFET 7nm

Capgemini; Sunnyvale (CA); On-site; USD 73,000 - 174,000; Full time

Job summary

Capgemini Engineering is seeking an experienced Analog and RF Layout Engineer to develop complex analog and mixed-signal ICs in advanced CMOS FinFET technologies. You will lead layout implementation, perform floorplanning, and collaborate with design and verification teams to ensure successful tape-outs in high-speed data applications.

The role requires 6+ years in analog/RF IC layout, proficiency with Cadence/Mentor/Synopsys tools, and strong knowledge of floorplanning, physical verification,

Qualifications

• Bachelor’s degree in Electrical Engineering or related discipline.
• 6+ years of experience in analog and RF IC layout.
• Experience with high-speed analog and mixed-signal designs in advanced CMOS FinFET technologies.
• Proficiency with Cadence, Mentor Graphics, or Synopsys EDA tools.
• Experience with transceivers, CMOS drivers, high-speed data converters, or PLLs.
• Strong knowledge of floorplanning, routing, chip integration, and physical verification.
• Understanding of thermal-aware layout, electromigration, and advanced physical-design practices.

Responsibilities

• Lead layout implementation for complex analog and RF ICs in advanced CMOS FinFET technologies, including 7nm and below.
• Perform floorplanning, block-level routing, and top-level chip assembly.
• Partner with design, verification, and product engineering teams to support successful tape-outs.
• Optimize layouts for performance, manufacturability, reliability, and silicon quality.
• Apply thermal-aware design and electromigration mitigation techniques.
• Support physical verification, design reviews, and design-rule compliance.

Skills

Analog RF layout

Floorplanning

Physical verification

Thermal-aware design

Electromigration mitigation

Transceivers/high-speed data paths

CMOS FinFET knowledge

High-speed data converters

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Synopsys

Job description

Capgemini Engineering is seeking an experienced Analog and RF Layout Engineer to develop complex analog and mixed-signal ICs in advanced CMOS FinFET technologies. You will lead layout implementation, perform floorplanning, and collaborate with design and verification teams to ensure successful tape-outs in high-speed data applications.

The role requires 6+ years in analog/RF IC layout, proficiency with Cadence/Mentor/Synopsys tools, and strong knowledge of floorplanning, physical verification,