Pre-Silicon IP Verification Engineer — PLL/FLL

Intel Corporation; Austin (TX); Hybrid; USD 122,000 - 173,000; Full time

Benefits offered by this job

Hybrid work model

Stock bonuses

Competitive pay and benefits

Job summary

Intel Corporation seeks an IP Design Verification Engineer within its Central Engineering Group to verify clock generator IPs (PLL/FLL) end-to-end, from test benches to pre-silicon debugging. You will build verification environments and collaborate closely with RTL and analog teams.

Responsibilities include developing tests in SystemVerilog/UVM, maintaining verification infrastructure, and ensuring conformance to microarchitectural specs. Hybrid work model in the US offered.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field with 4+ years of experience; or
• Master's degree with 3+ years; or
• PhD with 1+ year of experience.

Responsibilities

• Develop test benches, verification environments, and tests using SystemVerilog and UVM.
• Perform functional verification for clock generator IPs (PLL/FLL) against specifications.
• Maintain and refine verification infrastructure for multiple IP generations.
• Debug and root-cause pre-silicon issues within the verification environment.
• Document test plans and participate in technical reviews with design teams.
• Collaborate with architects, RTL developers, and analog design teams to improve verification.

Skills

SystemVerilog

UVM

Python

Perl

EDA tools

Design verification

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

SystemVerilog

UVM

Scripting (Python, Perl)

Job description

Intel Corporation seeks an IP Design Verification Engineer within its Central Engineering Group to verify clock generator IPs (PLL/FLL) end-to-end, from test benches to pre-silicon debugging. You will build verification environments and collaborate closely with RTL and analog teams.

Responsibilities include developing tests in SystemVerilog/UVM, maintaining verification infrastructure, and ensuring conformance to microarchitectural specs. Hybrid work model in the US offered.