Senior Analog & RF IC Layout Engineer — FinFET 7nm

Capgemini; Santa Clara (CA); In loco; USD 73.000 - 174.000; Tempo pieno

Vantaggi offerti da questo lavoro

Paid time off

Holidays

Personal days

Sick leave

Medical coverage

401(k) plan

Disability insurance

Employee assistance

Descrizione del lavoro

Capgemini Engineering is seeking an experienced Analog and RF Layout Engineer to develop complex analog and mixed-signal ICs in advanced CMOS FinFET technologies. You will lead layout implementation, floorplanning, and chip assembly for high-performance silicon used in communications and data applications.

You will collaborate with design and verification teams to ensure successful tape-outs, optimize for manufacturability and silicon quality, and apply thermal-aware design and electromigration

Competenze

• Bachelor's degree in Electrical Engineering or related discipline.
• 6+ years of analog and RF IC layout experience.
• Experience with high-speed analog/mixed-signal designs in FinFET tech.
• Proficiency with Cadence, Mentor Graphics, or Synopsys EDA tools.
• Experience with transceivers, CMOS drivers, high-speed data converters, or PLLs.
• Strong floorplanning, routing, chip integration, and physical verification knowledge.
• Understanding of thermal-aware layout and electromigration practices.

Mansioni

• Lead layout implementation for analog and RF ICs in FinFET tech.
• Perform floorplanning, block-level routing, and top-level chip assembly.
• Collaborate with design, verification, and product teams for tape-outs.
• Optimize layouts for performance, manufacturability, and silicon quality.
• Apply thermal-aware design and electromigration mitigation techniques.
• Support physical verification, design reviews, and design-rule compliance.

Conoscenze

Analog layout

RF layout

Floorplanning

Routing

Physical verification

Thermal-aware design

Electromigration mitigation

CMOS FinFET

Collaboration

Formazione

Bachelor's degree in Electrical Engineering

Strumenti

Cadence

Mentor Graphics

Synopsys EDA tools

Descrizione del lavoro

Capgemini Engineering is seeking an experienced Analog and RF Layout Engineer to develop complex analog and mixed-signal ICs in advanced CMOS FinFET technologies. You will lead layout implementation, floorplanning, and chip assembly for high-performance silicon used in communications and data applications.

You will collaborate with design and verification teams to ensure successful tape-outs, optimize for manufacturability and silicon quality, and apply thermal-aware design and electromigration