Pre-Silicon IP Verification Engineer for PLL/FLL

Intel Corporation; Folsom (CA); Hybrid; USD 122,000 - 173,000; Full time

Benefits offered by this job

Health benefits

Stock bonuses

Vacation

Job summary

Intel Corporation’s Central Engineering Group is seeking an IP Design Verification Engineer to ensure clock generator IPs (PLL/FLL) meet stringent specifications. You will build verification environments, write tests in SystemVerilog/UVM, and debug pre-silicon issues to guarantee quality across Intel's product lines.

In this role, you will collaborate with architects, RTL and analog teams, maintain verification infrastructure, and contribute to architectural feature refinement for scalable IP

Qualifications

• Bachelor's/Master/PhD with relevant experience as specified.
• Experience with UVM, SystemVerilog and EDA tools.
• Strong scripting and verification methodology knowledge.

Responsibilities

• Develop test benches, verification environments, and tests using System Verilog and UVM to ensure comprehensive IP validation
• Perform functional verification for clock generator IPs such as PLL and FLL, ensuring conformance to microarchitecture specifications
• Maintain and refine verification infrastructure and methodologies for multiple IP generations
• Debug and root-cause pre-silicon issues within the verification environment
• Document test plans and participate in technical reviews with design teams
• Collaborate cross-functionally with architects, RTL developers, and analog design teams to enhance verification of architectural and microarchitectural features
• Lead Mixed Signal Validation activities, including AMS simulations, schematic debugging, and resolving cross-functional issues
• Contribute to the definition and refinement of architectural and microarchitectural features for IP design

Skills

SystemVerilog

UVM

Python

Perl

Test benches

Debugging

Cross-functional collaboration

Education

Bachelor's Degree in Electrical or Computer Engineering or related field

Master's Degree in Electrical or Computer Engineering or related field

PhD in Electrical or Computer Engineering or related field

Tools

EDA tools

Job description

Intel Corporation’s Central Engineering Group is seeking an IP Design Verification Engineer to ensure clock generator IPs (PLL/FLL) meet stringent specifications. You will build verification environments, write tests in SystemVerilog/UVM, and debug pre-silicon issues to guarantee quality across Intel's product lines.

In this role, you will collaborate with architects, RTL and analog teams, maintain verification infrastructure, and contribute to architectural feature refinement for scalable IP