AI-Driven Silicon Tapeout Signoff Engineer

Voltai; Palo Alto (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Voltai is seeking a senior physical verification engineer in the Palo Alto area to own signoff on real silicon programs and guide AI-driven signoff improvements. You will collaborate with top semiconductor partners and drive reliability checks across block and full-chip levels.

You will perform DRC/LVS/ERC signoffs, IR drop and electromigration analyses, and build automation to streamline tapeouts while partnering with engineering teams to fix signoff issues and ensure robust silicon.

Qualifications

• 5+ years of physical verification or signoff on production tapeouts.
• Deep experience with Calibre or IC Validator.
• Experience with RedHawk or Voltus for IR/EM analysis.
• Strong understanding of advanced node foundry rule decks.
• Scripting: Tcl, Python, or SVRF.

Responsibilities

• Own DRC, LVS, ERC, and antenna signoff at block and full-chip level.
• Run and sign off IR drop, electromigration, and power integrity analysis.
• Debug and drive fixes for signoff violations with physical design teams.
• Manage tapeout checklists and foundry deliverables.
• Build automation for signoff runs, triage, and reporting.
• Help define how AI can triage and fix signoff violations.

Skills

Physical verification

Signoff experience

Calibre

IC Validator

RedHawk/Voltus

Scripting (Tcl/Python/SVRF)

Tools

Calibre

IC Validator

RedHawk

Voltus

SVRF

Job description

Voltai is seeking a senior physical verification engineer in the Palo Alto area to own signoff on real silicon programs and guide AI-driven signoff improvements. You will collaborate with top semiconductor partners and drive reliability checks across block and full-chip levels.

You will perform DRC/LVS/ERC signoffs, IR drop and electromigration analyses, and build automation to streamline tapeouts while partnering with engineering teams to fix signoff issues and ensure robust silicon.