Design Verification Engineer – AI-Driven ASICs & Tapeout

Normal Computing Corp.; Mountain View (CA); Vor Ort; USD 180.000 - 240.000; Vollzeit

Zusammenfassung

Normal Computing, based in Mountain View, is seeking a Design Verification Engineer to verify AI-enabled ASICs and raise the bar for verification flows. You will work on thermodynamic ASIC verification, testbench environments, and coverage to tapeout, applying advanced DV techniques.

The ideal candidate has 5+ years in digital verification at a semiconductor or EDA company, deep SystemVerilog/UVM expertise, and hands-on experience with vManager, Xcelium, and Jasper, plus Python or Perl

Qualifikationen

• 5+ years of experience in digital verification in semiconductors or EDA.
• Proficient with SystemVerilog and UVM methodology.
• Experience with EDA tools such as vManager, Xcelium, Jasper.
• Strong Python or Perl scripting skills.
• End-to-end design verification experience including test plans and stimulus generation.
• Excellent verbal and written communication for design reviews and debugging.

Aufgaben

• Verify internal silicon testbenches, assertions, and coverage from design documents through tapeout.
• Review AI-generated verification collateral and help define quality metrics.
• Set up and evaluate EDA tools, ensuring usability on shared computing resources internally.

Kenntnisse

Digital verification

SystemVerilog

UVM

Python scripting

Perl scripting

Excellent communication

Tools

vManager

Xcelium

Jasper

EDA verification tools

Jobbeschreibung

Normal Computing, based in Mountain View, is seeking a Design Verification Engineer to verify AI-enabled ASICs and raise the bar for verification flows. You will work on thermodynamic ASIC verification, testbench environments, and coverage to tapeout, applying advanced DV techniques.

The ideal candidate has 5+ years in digital verification at a semiconductor or EDA company, deep SystemVerilog/UVM expertise, and hands-on experience with vManager, Xcelium, and Jasper, plus Python or Perl