Physical Verification & Signoff Engineer

Voltai; Palo Alto (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Voltai is seeking a senior physical verification engineer in the Palo Alto area to own signoff on real silicon programs and guide AI-driven signoff improvements. You will collaborate with top semiconductor partners and drive reliability checks across block and full-chip levels.

You will perform DRC/LVS/ERC signoffs, IR drop and electromigration analyses, and build automation to streamline tapeouts while partnering with engineering teams to fix signoff issues and ensure robust silicon.

Qualifications

• 5+ years of physical verification or signoff on production tapeouts.
• Deep experience with Calibre or IC Validator.
• Experience with RedHawk or Voltus for IR/EM analysis.
• Strong understanding of advanced node foundry rule decks.
• Scripting: Tcl, Python, or SVRF.

Responsibilities

• Own DRC, LVS, ERC, and antenna signoff at block and full-chip level.
• Run and sign off IR drop, electromigration, and power integrity analysis.
• Debug and drive fixes for signoff violations with physical design teams.
• Manage tapeout checklists and foundry deliverables.
• Build automation for signoff runs, triage, and reporting.
• Help define how AI can triage and fix signoff violations.

Skills

Physical verification

Signoff experience

Calibre

IC Validator

RedHawk/Voltus

Scripting (Tcl/Python/SVRF)

Tools

Calibre

IC Validator

RedHawk

Voltus

SVRF

Job description

About Voltai

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

About Voltai

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

About The Team

Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About This Role

You’ll be the last line of defense before tapeout. You’ll own physical verification and reliability signoff on real silicon programs with leading semiconductor companies while helping Voltai's AI learn to find and fix signoff issues.

What You’ll Do

• Own DRC, LVS, ERC, and antenna signoff at block and full-chip level.
• Run and sign off IR drop, electromigration, and power integrity analysis.
• Debug and drive fixes for signoff violations with physical design teams.
• Manage tapeout checklists and foundry deliverables.
• Build automation for signoff runs, triage, and reporting.
• Help define how AI can triage and fix signoff violations.

What We’re Looking For

• 5+ years of physical verification or signoff experience on production tapeouts.
• Deep experience with Calibre or IC Validator.
• Experience with RedHawk or Voltus for IR/EM analysis.
• Strong understanding of foundry rule decks at advanced nodes.
• Tcl, Python, or SVRF scripting.

Bonus Points

• Experience with 2.5D/3D packaging or chiplet integration signoff.
• Direct foundry interface experience.
• Interest in AI-assisted design tools.