AI Accelerator Design Verification Engineer - Intern

RosaicLabs Inc; Santa Clara (CA); On-site; USD 28,000 - 41,000; Part time

Job summary

RosaicLabs Inc in Santa Clara, CA is seeking a student intern or co-op to verify accelerator designs, owning verification environments from test plan through coverage closure. You'll gain hands-on experience with chip design and verification in a collaborative hardware team.

You will write SystemVerilog/UVM testbenches, build scoreboards, triage failures with mentors, and contribute to reviews and documentation of your verification results.

Qualifications

• Pursuing BS/MS in Electrical/Computer Engineering, CS or related field.
• Familiarity with digital design and verification concepts.
• Hands-on SystemVerilog experience including testbench development (UVM preferred).
• Understanding of end-to-end ASIC design flow and VLSI concepts.

Responsibilities

• Develop verification plans for the accelerator with a mentor.
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus.
• Build tests, scoreboards, and reference models; close coverage.
• Triage and root-cause failures with RTL designers with mentorship.
• Participate in design and verification reviews and document results.

Skills

SystemVerilog

UVM

Scripting (Python, Perl, Tcl)

Education

BS/MS in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Python

Perl

Tcl

Job description

Join our hardware team as an intern or co-op verifying the accelerator, with hands-on ownership of verification environments from test plan through coverage closure and bring-up.

Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together.

What you'll do

• Work with your mentor to develop verification plans for the accelerator
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
• Build tests, scoreboards, and reference models, and close functional and code coverage
• Triage and root-cause failures with RTL designers, with mentorship from senior engineers
• Participate in design and verification reviews and document your verification environment and results

Requirements

• Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
• Familiarity with verifying accelerator designs, such as: parallel datapaths and SIMD / SIMT / vector processing; numerical formats and computer arithmetic; data movement over DMA and memory interfaces
• Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
• Understanding of the end-to-end ASIC design flow and general VLSI concepts
• Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.