Physical Design Engineer, 3D Technology

Google; Sunnyvale (CA); On-site; USD 117,000 - 197,000; Full time

Job summary

Google is seeking a Physical Design Engineer, 3D Technology, to shape the future of AI/ML hardware acceleration. You will contribute to TPU architecture and its integration within AI/ML systems, collaborating with HW teams to push 3D integration boundaries and deliver high-performance ASIC/SoC designs.

You will drive 3D physical design methodologies, optimize across digital blocks, and participate in tapeout readiness, enabling Google's TPU innovations at scale.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• 4 years in physical design and 3D integration tech (3D-IC, 2.5D, TSV).
• Experience with industry standard chip design tools (Synopsys, Cadence, Siemens EDA/Mentor).

Responsibilities

• Drive development of a leading edge 3D technology platform for ASICs/SoCs from design to test.
• Optimize digital blocks for performance, power, and area using physical design methods.
• Define methodologies by evaluating performance, power, and area across nodes.
• Collaborate with physical design, technology, circuits, and architecture teams and IP partners.
• Design and build custom transistor/gate-level circuits to support floorplanning.

Skills

3D integration

Physical design

Hardware architecture

VLSI design

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

Synopsys

Cadence

Mentor Graphics

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with physical design and 3D integration technologies, such as 3D-IC, 2.5D, chip stacking, vertical stacking, Integrity, or Through-Silicon Vias (TSV).
• Experience running industry standard tools for chip design, such as Synopsys, Cadence, Siemens EDA/Mentor Graphics.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Power, Performance, and Area (PPA) design trade-offs and optimizations in physical design spaces.
• Experience with advanced FinFET and gate-all-around (GAA) technology nodes, including enabling physical design flows in these nodes.
• Experience delivering optimized digital place-and-route blocks leading to product tapeouts.
• Experience with programming/scripting (e.g., TCL, Python, or Perl) for design flow automation.
• Understanding of standard cells, SRAMs, power, noise, and IR analysis.

About The Job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Physical Design Engineer, 3D Technology you will collaborate with technology, physical design, circuit design, and hardware architecture teams to overcome the slowing of Moore’s Law while delivering cutting-edge ASIC’s and SoC’s. You will help develop new 3D technology physical design methodologies to drive best product PPA by optimizing across technology, digital block implementation, clock distribution, floorplanning, circuits, memories, and third-party IPs. You will drive new physical design flows that co-optimize across the entire design methodology space including 3D and see these through from inception to maturity and tapeout. This will include high impact physical design innovations with Through-Silicon Vias (TSVs) requiring methodology and verification flow development and ratification. As part of this work, you will participate in the development of exceptional technology in high performance computing and ensure product success. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Salary

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits.

Responsibilities

Learn more about benefits at Google .

• Drive development of a leading edge 3D technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.
• Optimize digital blocks for performance, power, area, and reliability using physical design and circuit techniques.
• Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.
• Work with our physical design, technology, circuits, and architecture teams plus IP partners in advanced CMOS nodes.
• Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .