AI/ML TPU Compute RTL Design Engineer

Google LLC; Austin (TX); On-site; USD 138,000 - 197,000; Full time

Job summary

Google LLC in Austin, TX is seeking an experienced hardware design engineer to shape AI/ML acceleration through TPU architecture. You will verify complex digital designs with a focus on SystemVerilog RTL and integration within AI/ML systems.

You will collaborate with software, architecture, and cross-functional teams to deliver scalable silicon solutions powering Google's TPU products and related AI infrastructure.

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CS.
• 4 years of digital design experience using SystemVerilog RTL.
• Experience with Computer Architecture.

Responsibilities

• Develop and review Compute subsystem's design microarchitecture specifications.
• Write SystemVerilog RTL to implement ASIC logic per guidelines.
• Collaborate with DV teams to create test plans and verify RTL.
• Coordinate with physical design to meet timing and hardware constraints.

Skills

SystemVerilog RTL

Computer Architecture

Cross-functional collaboration

Education

Bachelor's degree or equivalent practical experience in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science with emphasis on computer architecture

Tools

SystemVerilog RTL

Job description

Google LLC in Austin, TX is seeking an experienced hardware design engineer to shape AI/ML acceleration through TPU architecture. You will verify complex digital designs with a focus on SystemVerilog RTL and integration within AI/ML systems.

You will collaborate with software, architecture, and cross-functional teams to deliver scalable silicon solutions powering Google's TPU products and related AI infrastructure.