3D IC Integration Design Enablement Engineer

GLOBALFOUNDRIES U.S. INC.; New York, Town of Malta (NY, NY); On-site; USD 65,000 - 146,000; Full time

Job summary

GlobalFoundries in Malta, New York, seeks an R&D design enablement engineer to drive 3D heterogeneous integration and packaging enablement for next-generation research efforts.

You will collaborate with R&D and fabrication teams on wafer-to-wafer and die-to-wafer bonding, TSV/TOV, and interposer development, contributing to design rules, LM/LVS requirements, and device models while traveling up to 10% as needed.

Qualifications

• Education – PhD with completed defended thesis or Master's in Electrical Engineering and Materials Science or related field from an accredited degree program.
• Must have at least an overall 3.0 GPA and proven good academic standing.
• Language Fluency - English (Written & Verbal).
• Travel - Up to 10%.

Responsibilities

• Publish Design Manual specifications based on failure modes identified for packaging required by the product lines in partnership with the unit process and R&D engineers.
• Advanced packaging liaison to the DM and PDK teams to translate packaging requirements to a device enablement specification.
• Develop expertise in drafting test vehicle content specifications and the associated tapeout process.
• Develop expertise in drafting test specifications for test vehicle content (macros).
• Collaborate with vendors and OSATs on design (test vehicles, masks).
• Facilitate advanced packaging design interactions between the product lines/fab teams and customers.
• Work and collaborate with other teams regarding different assignments as needed.

Skills

Leadership experience

Project management

Communication skills

Planning & organization

Education

PhD with defended thesis

Master's in Electrical Engineering and Materials Science

Job description

GlobalFoundries in Malta, New York, seeks an R&D design enablement engineer to drive 3D heterogeneous integration and packaging enablement for next-generation research efforts.

You will collaborate with R&D and fabrication teams on wafer-to-wafer and die-to-wafer bonding, TSV/TOV, and interposer development, contributing to design rules, LM/LVS requirements, and device models while traveling up to 10% as needed.