Standard Cell Library Design Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading technology firm in Singapore seeks a candidate to design and develop standard cell library foundation IP for silicon products. Responsibilities include generating EDA models, quality checks, and process automation. Ideal candidates should have a degree in Electrical/Electronic Engineering and solid experience in digital circuit design. Candidates with Masters and relevant experience or strong GPA fresh graduates are also welcome. This role requires collaboration within teams and excellent communication skills.

Qualifications

• 2+ years of related experience preferred, or fresh graduates with good GPA.
• Singapore Citizen/PR only.

Responsibilities

• Generate and verify library EDA models.
• Run regression and quality checks on library deliverables.
• Interface with design teams to support their requirements.
• Implement process automation for consistent throughput.

Skills

Digital or mixed-signal circuit design knowledge

Understanding of FinFet, RibbonFet/GAA process nodes

Familiarity with EDA tools

Experience with .lib syntax

Scripting using Unix, Perl, TCL or Python

Education

Bachelor's in Electrical/Electronic or Computer Engineering

Masters in relevant field

Tools

Virtuoso

Cadence Skill programming

Job description

Broadcom's Central Engineering Group builds the Foundation IP that powers Broadcom's leading silicon product families. In this position, the successful candidate will be part of the team responsible for the design, development and delivery of standard cell library foundation IP

Job Responsibilities:

• Generate and verify library EDA models
• Run regression and quality checks on library deliverables
• Interface with design teams to support their requirements
• Implement process automation for consistent and faster throughput (scripting)

Key Requirements:

• Digital or mixed-signal circuit design knowledge
• Understanding of cell layout or physical design
• Understanding of FinFet, RibbonFet/GAA process nodes
• Understanding of verilog, lef, liberty and other industry standard EDA models
• Familiarity with EDA tools used in STA and PnR
• Experience with .lib syntax including NLDM/CCS/LVF is a plus
• Experience with Virtuoso, Cadence Skill programming, scripting using Unix, Perl, TCL or Python is strongly desired

Qualifications & Experience:

• Bachelor's in Electrical/Electronic or Computer Engineering and 2+ years of related experience / Candidates with Masters and 1+ years of related experience / Fresh graduates with good GPA will be considered
• Singapore Citizen/PR only

Additional Qualifications:

• Excellent written and verbal communication skills
• Collaborate and work within and across teams